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IP / SOC Products News

• Dolphin Integration concentrates on cost-cutting with the Standard Cell Library HD-BTF for 65 nm processes (Friday May. 07, 2010)
  Fabless companies can seize the opportunity to decrease the area of their logic blocks by 5 to 10% with the highest-density Standard Cell Library available in the 65 nm technological process.
  
  
• Evatronix Introduces a 65C02 Chip Compatible Microprocessor IP Core (Thursday May. 06, 2010)
  Evatronix today announced the C65C02 – a 65C02 compatible microprocessor IP core that complies with the original 6502 Instruction Set Architecture by MOS Technology.
  
  
• Synopsys Unveils Ethernet Controller IP With New Audio Video Bridging Feature (Wednesday May. 05, 2010)
  Synopsys today announced the immediate availability of the DesignWare® Ethernet Quality-of-Service (QoS) Controller IP which implements the new IEEE specifications for audio video bridging (AVB) features.
  
  
• eMemory caters to market needs and offers a complete set of Multiple-Times-Programmable (MTP) Embedded Non-Volatile Memory solutions (Wednesday May. 05, 2010)
  eMemory’s Neobit OTP technology has been implementing into almost all process platforms in worldwide foundries. Just as Neobit technology’s fast growth has gained significant market share to retain number one popularization in the global OTP market, eMemory foresaw the future market needs and endeavored to the development of advanced embedded non-volatile memory technology, catering to customer needs with MTP solutions for large density and high endurance at a much lower cost.
  
  
• Synopsys Launches Industry's First MIPI DigRF v4 IP (Monday May. 03, 2010)
  Synopsys today announced the immediate availability of the DesignWare® MIPI® 4G DigRF(SM) Master Controller IP. By complementing its current silicon-proven DesignWare MIPI 3G DigRF Controller and PHY IP, Synopsys becomes the first vendor to offer a comprehensive IP portfolio for both the MIPI DigRF v3 and v4 standards.
  
  
• Microtronix introduces Scatter Gather DMA Engine for Altera PCIe Hard IP Cores (Monday May. 03, 2010)
  Microtronix today announced the release of their new Lancero Scatter-Gather DMA Engine for PCI Express for Altera® FPGA's incorporating PCI Express Hard IP cores. The kit provides the IP and Linux software drivers to implement a bidirectional Scatter-Gather Direct Memory Access (DMA) Engine for PCI Express interfaces on Linux host computer systems.
  
  
• New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces (Wednesday Apr. 28, 2010)
  Synopsys announced the availability of the high-performance DesignWare® Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and LPDDR2 SDRAM standards.
  
  
• Imagination's POWERVR VXD391 adds On2 VP6 and Real Video capabilities (Tuesday Apr. 27, 2010)
  Imagination Technologies announces the latest member of its video decode IP core family, POWERVR VXD391. An ultra low power, high performance 1080p HD hardware video decoder IP core with multi-standard multi-stream capabilities, VXD391 now features the most extensive range of standards supported by a single video decoder, essential for accelerating all forms of video content found on the internet today, including Real Video 8/9, On2 VP6, and Sorenson Spark.
  
  
• Imagination debuts full range of TV audio codecs (Tuesday Apr. 27, 2010)
  Imagination Technologies will be demonstrating its latest application platform solutions for high performance, low power multi-channel, multi-standard audio utilising its META multithreaded processor technologies at ESC 2010.
  
  
• Plurality Ltd. Announces the World's First Scalable 256 Multicore Processor for Wireless Infrastructure (Tuesday Apr. 27, 2010)
  Plurality announced today the world's first scalable 256 multicore processor for wireless infrastructure, the HyperCore™ family of low power, small footprint, ManyCore processor IP for wireless markets.
  
  
• ARM CoreSight Technology Extends Real-time System Visibility to All Software Developers (Tuesday Apr. 27, 2010)
  ARMannounced today the launch of the ARM® CoreSight™ System Trace Macrocell and Trace Memory Controller providing software and system on chip (SoC) developers with a cost effective, industry-standard debug and optimization SoC platform solution.
  
  
• Elliptic Technologies Shatters Industry Latency Benchmark With New Ethernet Security Engine (Monday Apr. 26, 2010)
  Elliptic today announced that it has released the LLP-06 Ultra Low Latency MACsec security engine which offers a dramatic 30 percent improved latency (delay) performance over existing solutions available today.
  
  
• TAKUMI Launches GV330 The New Dedicated Vector Graphics IP Core with Significantly Enhanced Rendering Performance and Functionalities (Thursday Apr. 22, 2010)
  TAKUMI announced today official release of the new GSHARK-TAKUMI GV330 Vector Graphics Accelerator IP Core (“GV330”) compliant with OpenVG1.1, a graphics API standard for embedded systems.
  
  
• Tensilica Introduces Third Generation ConnX 545CK 8-MAC VLIW DSP Core (Thursday Apr. 22, 2010)
  Tensilica today introduced its third generation ConnX 545CK 8-MAC (multiply-accumulate) VLIW (very long instruction word) DSP (digital signal processor) core for system-on-chip (SOC) designs. Improvements in this third generation dataplane processor (DPU) core deliver up to 20 percent faster clock speed, 11 percent smaller die and up to 30 percent lower power consumption.
  
  
• Faraday Announces the Commercial Availability of PCIe Gen2 Endpoint Controller (Wednesday Apr. 21, 2010)
  Faraday Technology today announced the availability of its commercial PCI Express (PCIe) Gen2 endpoint (EP) controller. This new component is fully compliant with the industry standard PCIe Based Specification 2.0 at the maximum speed of 5.0GT/s.
  
  
• Virage Logic Extends Technology Leadership by Qualifying the Industry's First Million-Cycle CMOS-Based MTP NVM IP (Wednesday Apr. 21, 2010)
  Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry's trusted IP partner, today announced that its AEON® MTP (Multiple Time Programmable) NVM (non-volatile memory) EEPROM IP has been qualified for a million cycles at an elevated temperature of 105°C in a standard 250-nanometer (nm), 5V CMOS process.
  
  
• Blue Wonder Communications' BWC200 Passed First IOT Tests against ZTE Environment (Tuesday Apr. 20, 2010)
  Blue Wonder Communications has entered into the interoperability testing phase with its recently announced LTE IP product BWC200. During this test session against ZTE’s test environment the BWC200 has successfully passed uplink, downlink and synchronization tests via antenna over the air at up to 20 MHz bandwidth.
  
  
• Customization for market needs comes to a turning point with Dolphin integration Codec Configurator (Friday Apr. 16, 2010)
  Dolphin Integration today reveals its breakthrough configurator for providing fast and safe instances of high performance audio converters from their JAXAUDIO kit of pre-characterized mixed signal blocks.
  
  
• IP Cores, Inc. Announces a New Version of the RSA Public Key Accelerator (Thursday Apr. 15, 2010)
  
  
  
• CoreEL Launches Advanced Video Decoding Solutions (Wednesday Apr. 14, 2010)
  CoreEL Technologies today announced the availability of three new video decoding IP solutions that include, an integrated Broadcast grade H.264 and MPEG-2 HD decoder solution on a single Xilinx® Virtex®-6FPGA., a MPEG-2 4:2:2@HL 1080p60 decoding IP Core working on the high performance Virtex-6 FPGA and a H264/MPEG2 decoding solution working on a low-cost Spartan®-6 FPGA.
  
  
• CAST Offers the First 12-bit JPEG Extended Sequential, DICOM-Compatible IP Core (Tuesday Apr. 13, 2010)
  CAST, Inc. now offers the only encoder core that supports both the Baseline (8-bit) and Extended Sequential (12-bit) modes of the JPEG image compression standard. This plus a fast, compact design make the new JPEG-E-X IP core one of the best available lossy compression encoders for medical imaging, reconnaissance, and other applications where exceptional image detail is required.
  
  
• Virage Logic Extends Non Volatile Memory Leadership; Announces AEON(R) Multi-Time Programmable Parallel NVM Qualified in TSMC 130nm G Process (Tuesday Apr. 13, 2010)
  Virage Logic today expanded its industry leading portfolio of multi-time programmable (MTP) non-volatile memory (NVM) with the qualification of AEON MTP Parallel NVM at TSMC. AEON MTP Parallel NVM now available in 130-nanometer (nm) G process is targeted at analog mixed-signal applications now migrating from 180nm down to 130nm.
  
  
• Virage Logic Announces Availability of a Full Suite of 28nm SiWare Memory Compilers and Rollout of SiWare Logic Libraries for Leading Edge Customers (Tuesday Apr. 13, 2010)
  Virage Logic extends its leadership position by announcing a full suite of 28-nanometer (nm) memory compilers and logic libraries on TSMC’s High-K Metal Gate (28nm HP) process. Following on the early success of their 40nm-node design, two of the company’s longstanding customers have already adopted the 28nm SiWare Memory technology.
  
  
• IP Cores, Inc. Announces Shipment of a New Version of its SHA Family of Hash Cores (Thursday Apr. 08, 2010)
  IP Cores has announced first shipments of a new version of IP cores from its SHA family of cores performing cryptographic hash algorithms. Cryptographic hashes are widely used in the secure communication protocols.
  
  
• OptNgn Releases 264 FFT FPGA Library Elements that are High Performance, Vendor Independent, and Instantly Downloadable (Wednesday Apr. 07, 2010)
  Altera, Xilinx and Mentor Graphics Precision Synthesis users can instantly download, at a cost of $60-$600, streaming FFT IP that will process up to 250 Million complex samples per second.
  
  
• Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards in a Single PHY (Wednesday Apr. 07, 2010)
  Synopsys today announced availability of the DesignWare™ DDR multiPHY which is designed to support a broad range of DDR SDRAM standards in a single PHY without sacrificing power consumption or silicon area.
  
  
• CEVA Releases SATA3.0 IP for 6Gbps SSD Applications (Wednesday Apr. 07, 2010)
  CEVA today announced the availability of the CEVA-SATA3.0 Device Controller IP. The IP has already been licensed to a leading FLASH memory semiconductor manufacturer for use in their future SSD designs.
  
  
• Novocell Semiconductor Announces the Release of 2nTP; the Industry's First Multi-Time Programmable Antifuse Bit Cell (Wednesday Apr. 07, 2010)
  Novocell today announced the release of 2nTP; the industry’s first multi-time write antifuse technology. 2nTP allows 2n times programming, supporting 2, 4, or 8 times write. For the same number of writes 60% area savings can be achieved versus using multiple cascaded OTP blocks for the same number of writes.
  
  
• Intilop (formerly intelop) releases new fully integrated FPGA-SOC-Platform with TOE, PCI Express and system peripherals that raise the bar in TOE system integration (Thursday Apr. 01, 2010)
  Intilop today announced Xilinx V5 and V6 FPGA based development platforms offering a total system solutions for their TCP offload engine SoC IP. The FPGA embedded development platform integrates various features of TCP/IP protocol in hardware which provide differentiated levels of TCP/IP performance improvement.
  
  
• Synopsys' DesignWare SuperSpeed USB 3.0 IP Receives USB-IF Certification (Thursday Apr. 01, 2010)
  Synopsys today announced that its DesignWare® SuperSpeed USB (USB 3.0) Solution including Controller and PHY IP successfully passed the USB Implementers Forum (USB-IF) SuperSpeed USB certification.