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IP / SOC Products News

• Elliptic Technologies Offers First Security Engine for Multi-Core System-On-Chip Designs (Wednesday Mar. 31, 2010)
  Elliptic Technologies today announced that it has released the latest version of its CLP-600 Security Protocol Accelerator (SPAcc) which now includes the ability to support multiple processor cores from a single hardware security engine.
  
  
• Faraday Launches Its USB 3.0 PHY in UMC 90nm (Tuesday Mar. 30, 2010)
  Faraday Technology today announced the availability of its commercial USB 3.0 physical layer (PHY) at UMC 90nm high-speed (HS) process. With smaller size and lower power consumption than peers', this new component is developed based upon USB 3.0 version 1.0 specification functionally and electrically, achieving the maximum speed of 5.0Gbps.
  
  
• MIPS Technologies and Virage Logic Partner to Offer Optimized Embedded Memory IP (Monday Mar. 29, 2010)
  MIPS and Virage Logic today announced they are teaming to offer optimized embedded memory IP for joint customers. With SRAM memory instances from the Virage Logic ASAP 90nm and SiWare 65GP High Density SRAM compiler families specifically optimized for MIPS32® processors, customers can speed development of complex SoCs targeted for Blu-ray DVD, HDTV, IPTV, set-top box and broadband customer premises equipment (CPE) devices.
  
  
• Dolphin Integration announces the availability of a brand new Front End generator: spRAM Haumea for the 130 nm G process (Friday Mar. 26, 2010)
  Dolphin Integration’s strategy for the 130 nm technological process is to release a Register Bank Panoply for SoC designers with the capability to generate instances from 1 bit up to 512 kbits.
  
  
• Kilopass First to Offer Logic Non-Volatile Memory (NVM) in TSMC 40nm and 45nm Low-Power (LP) Processes (Thursday Mar. 25, 2010)
  Kilopass Technology today announced that its XPM™ embedded one-time programmable (OTP) NVM technology is the first to complete TSMC IP-9000 Level 4 qualification and skew characterization in both the TSMC™ 40nm and 45nm low-power (LP) process technologies.
  
  
• Intilop corporation (formerly intelop) releases a series of new TOE IP solutions that offer the fastest with lowest latency, highest TCP/IP performance and smallest size (Wednesday Mar. 24, 2010)
  Intilop today announced a host of solutions for their TCP offload engine SoC IP.
  
  
• Virage Logic Introduces Industry Leading MIPI D-PHYs and Controllers on 40LP Process (Wednesday Mar. 24, 2010)
  Virage Logic today announced the availability of its SiPro(TM) MIPI Rx D-PHY and MIPI Tx D-PHY as well as CSI Rx (camera serial interface receiver) and DSI Tx (display serial interface transmitter) controllers on the 40LP process node in Q2 of this year which are based on the production proven D-PHYs announced last year.
  
  
• IP Cores, Inc. Ships an AES Encryption Core Supporting the EAX' Encryption Mode of ANSI C12.22 (Wednesday Mar. 24, 2010)
  IP Cores, Inc. has shipped an AES encryption IP core supporting the new EAX’ encryption mode. EAX mode of operation for cryptographic block ciphers implements authenticated encryption with Associated Data (AEAD) algorithm to simultaneously provide both authentication and privacy for the communication link (so called authenticated encryption) via a two-pass operation, with one pass delivering privacy and one authenticity for each message.
  
  
• Dolphin Integration completes their catalog of Standard Cell Libraries with a new stem optimized for low leakage: LL-BTF (Monday Mar. 22, 2010)
  Dolphin Integration’s strategy is to offer to Standard Cell Users a bunch of specialized stems ultimately optimized for one prime criterion. The HD-BTF stem optimized for high density comes first and is already available for major foundries in the 180 nm, 130 nm and 65 nm technological processes.
  
  
• Vitesse's New Forward Error Correction Technology Accelerates Migration to 100G (Monday Mar. 22, 2010)
  Vitesse today announced immediate availability of its enhanced forward error correction (eFEC) technology for implementation in ASICs or FPGAs. Vitesse's new, patented Continuously Interleaved BCH (CI-BCH™) eFEC code offers the highest performing hard decision eFEC available today and is the industry’s only eFEC implementable in single FPGA form at 100G.
  
  
• Intilop (formerly Intelop) corporation's TCP Offload engine IP solution delivers amazing TCP/IP throughput as reported by customers in system level performance testing (Monday Mar. 22, 2010)
  This second generation Customizable Full TCP offload Engine also integrates GEMAC, ARP module, RDMA engines, PLB/405 bus interfaces. It is capable of implementing/accelerating hundreds of simultaneous TCP sessions, delivering 800 % -1500% performance improvement over TCP/IP software implementations.
  
  
• Arteris Announces Support For New ARM AMBA 4 Interconnect Specification (Thursday Mar. 18, 2010)
  Arteris today announced support for the new ARM(R) AMBA(R) 4 specification. Arteris and ARM are working together to ensure interoperability between the AMBA 4 AXI(TM) 4 interface protocol and the Arteris Network on Chip (NoC), and are partnering to deliver optimal system performance for SoC designers using AXI4 protocol-compliant IP together with Arteris NoC interconnect technology.
  
  
• ViaSat Announces New 100G Optical Transport Forward Error Correction (FEC) Products and Digital Signal Processing Services (Wednesday Mar. 17, 2010)
  ViaSat is introducing a family of forward error correction (FEC) products for 100G optical transport. These FEC and digital signal processing (DSP) products, available in either FPGA or ASIC cores, can provide major cost savings over optical compensation techniques, increase optical channel capacity, and extend the range of transmission for optical cables.
  
  
• Innovative Silicon's Z-RAM Technology Meets Low Voltage and Bulk Silicon Requirements of DRAM Memory Manufacturers (Wednesday Mar. 17, 2010)
  Innovative Silicon today announced two major breakthroughs to its Z-RAM technology. First, bit cell operating voltage has been reduced to below one volt (1V), making it the industry’s lowest-voltage FB memory bit cell and the first to be on-par with traditional DRAM voltages. Second, Z-RAM technology is now constructed on bulk silicon – without the requirement for expensive silicon on insulator (SOI) substrates – by using the 3D transistor structures preferred by the major DRAM manufacturers.
  
  
• ARM to Reshape the Smartcard Market with Industry's Smallest and Most Energy-Efficient Securcore SC000 Processor (Tuesday Mar. 16, 2010)
  ARM today announced the launch of the highly compact and energy-efficient ARM® SecurCore™ SC000™ processor, designed specifically for the highest volume smartcard and embedded security applications.
  
  
• Ensphere Solutions Announced the Availability of a High Accuracy Temperature Sensor Intellectual Property (Monday Mar. 15, 2010)
  Ensphere Solutions’ new ESI-P3010 is a power and area optimized IP implemented in mainstream processes such as TSMC 65nm-G and TowerJazz 180 nm. This core consists of a temperature sensor connected to one of the eight inputs of an analog multiplexer.
  
  
• Evatronix Optimizes its I2S Audio Interface Controller by Adding TDM Support and Single Channel Operation (Monday Mar. 15, 2010)
  Evatronix SA, announced today the introduction of the I2S-SC controller IP. It is compatible with the Philips I2S specification and all its modes; however, it reduces the number of supported channels from eight to one and introduces the Time Division Multiplexing (TDM) mechanism for more efficient multi-channel handling.
  
  
• Tensilica Introduces Third Generation Diamond Standard Controllers Optimized for Low Power, High Performance Applications (Monday Mar. 15, 2010)
  Tensilica today introduced its third generation of Diamond Standard controllers. Improvements in this third generation of Diamond Standard controllers deliver up to 15 percent faster clock speed, up to 20 percent smaller die area and up to 15 percent less power consumption.
  
  
• Noesis Technologies releases fully configurable N-point FFT/IFFT core (Friday Mar. 12, 2010)
  Noesis Technologies announced today the immediate availability of its N-point fully configurable FFT/IFFT core (ntBFFT). ntBFFT core is a fully configurable solution that performs the FFT and IFFT transform. It is on-the-fly programmable in terms of transform size and type. It supports complex input/output and the results are output in normal order.
  
  
• Sonics Announces Support for AMBA 4 Specification (Thursday Mar. 11, 2010)
  Sonics, Inc.®, announced that its on-chip communications solutions will support phase one of the new AMBA® 4 protocol unveiled this week by ARM. This ensures that chip designers who currently use the AMBA 3 specification will have an easy migration path to AMBA 4 products as design upgrades are rolled out. ARM indicates further enhancements to the specification will be available later this year.
  
  
• Silicon Hive Introduces HiveLogic Configurable Parallel Processing Platform (Wednesday Mar. 10, 2010)
  Silicon Hive today announced HiveLogic, a configurable parallel processing platform enabling embedded programmable solutions for system-on-chips at unprecedented silicon area utilization and power consumption efficiency. The underlying parallel processing technology has already been deployed by Silicon Hive in mass-consumer solutions for connected multimedia applications in smart phones and digital televisions.
  
  
• POSEDGE announces Ultra Speed, High Performance, and Low Gate Count SD/SDIO/eMMC Host Controller IP (Tuesday Mar. 09, 2010)
  Posedge has announced the availability of soft IP Core that performs SD/SDIO/eMMC Host controller functionality. The Posedge SD/SDIO/eMMC Host Controller Core is highly configurable and is compliant with SD Host 3.0, SDIO 3.0, and eMMC4.4 specification.
  
  
• Altera's Stratix IV FPGAs Pass Interlaken Interoperability Test (Monday Mar. 08, 2010)
  Altera today announced its Stratix® IV FPGAs passed the Interlaken Alliance's device interoperability testing. Altera passed interoperability testing using a Stratix IV GT FPGA development board along with Altera's internally developed Interlaken intellectual property (IP) core.
  
  
• CSEM introduces a new generation of ultra low power DSP RISC cores for portable applications (Tuesday Mar. 02, 2010)
  The icyflex family of ultra low power 16/32-bit RISC processor cores developed by CSEM, the Swiss Center for Electronics and Microtechnology, offers a flexible ar-chitecture that allows for different combinations of control and DSP functionality. Three silicon-proven cores are so far available, consuming as little as 6 μW/MHz.
  
  
• Crack Semiconductor Releases Performance Data For The CS256-ECC and CS1024-PKA Processors (Tuesday Mar. 02, 2010)
  Crack Semiconductor's CS256-ECC and CS1024-PKA processors offer amazing performance for GF(p) Elliptic Curve operations up to 512-bits based. . The CS256-ECC is a smaller, ECC-only variant of the CS1024-PKA processor with the same ECC performance.
  
  
• iSine Inc. Releases Extreme ECC(tm) for NAND Flash SOC's optimized for ASIC and Xilinx FPGA implementation (Tuesday Mar. 02, 2010)
  iSine Inc. has announced the full release of its Extreme ECC technology that meets the needs of the most demanding error correction environments. The Extreme ECC technology supports traditional SLC and MLC NAND Flash requirements, in addition to Standard ONFI 2.1 and Toggle Mode NAND Flash interface demands.
  
  
• Noesis Technologies releases NIST FIPS-197 compliant Low Power AES IP core (Monday Mar. 01, 2010)
  Noesis Technologies announced today the immediate availability of its NIST FIPS-197 compliant Advanced Encryption Standard IP core (ntAES8). ntAES8 core can be programmed to encrypt or decrypt 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key.
  
  
• Dolphin Integration widens their catalog with libraries targeting both Low Power and High Speed (Monday Feb. 22, 2010)
  In 2010, Dolphin Integration focuses their product offering on both their long-established know-how on Low Power designs for embedded memories and standard cell libraries. New architectures are released from the 130 nm technological process down to 40 nm LP with versions optimized for high speed.
  
  
• ARM Launches Class-Leading Cortex-M4 Processor For High Performance Digital Signal Control (Monday Feb. 22, 2010)
  ARM today announced the launch of the innovative Cortex™-M4 processor to provide a highly efficient solution for digital signal control (DSC) applications, while maintaining the industry leading capabilities of the ARM® Cortex-M family of processors for advanced microcontroller (MCU) applications.
  
  
• SiliconGate Introduces the First Ultra Fast DC/DC IP for Process Technologies Ranging from 0.25um to 40nm (Friday Feb. 19, 2010)
  SILICONGATE today announced the availability of silicon-proven SGC67120, the first in a family of synchronous step-down DC/DC converters designed to operate from a 1.8V to 5.5V input and deliver up to 3A to 0.6V to 3.6V outputs. With an extremely fast 1.5µs response time, this new converter promises to reduce the external capacitor size and overall solution cost for portable applications.