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IP / SOC Products News

• SoftJin announces High Performance JPEG Encoder and Decoder IP (Thursday Feb. 18, 2010)
  SoftJin announces JPEG Encoder and Decoder IP. SoftJin’s JPEG encoder IP is a high performance RTL solution and capable of encoding Still Images as well as Video stream with SD, VGA and HD resolution.
  
  
• Elliptic Technologies Offers Solution to Longstanding Security challenge - implementing asymmetric or public key cryptography (Tuesday Feb. 16, 2010)
  Elliptic today announced that it has released a comprehensive solution to perhaps the most difficult challenge today facing designers in security – implementing asymmetric or public key cryptography.
  
  
• Intelop corporation's TCP Offload engine IP delivers amazing TCP/IP throughput (Tuesday Feb. 16, 2010)
  Intelop corporation’s TCP Offload engine IP delivers amazing TCP/IP throughput as reported by customers in system level performance testing. This second generation Customizable Full TCP offload Engine also integrates GEMAC, ARP module, RDMA engines, PLB/405 bus interfaces running at 2-Gbps. It is capable of implementing/ accelerating hundreds of simultaneous TCP sessions, delivering 800 % -1500% performance improvement over TCP/IP software implementations.
  
  
• Imagination extends standards supported on ENSIGMA UCCP310 with Wi-Fi and ATSC, demonstrates SoC test chip (Monday Feb. 15, 2010)
  Imagination Technologies is demonstrating two of Imagination's latest ENSIGMA UCCP310 IP platforms running real time Wi-Fi and ATSC integrated on an advanced SoC test chip at MWC 2010 in Barcelona (15-18 February 2010).
  
  
• CEVA Unveils Industry's First Multipurpose Programmable HD Video and Image Processing Platform for Connected Multimedia Devices (Monday Feb. 15, 2010)
  CEVA today unveiled CEVA-MM3000™, a fully programmable, HD video and imaging platform specifically designed for the connected generation of portable multimedia and home entertainment devices.
  
  
• ArrayComm and CEVA Partner to Develop LTE Wireless Infrastructure Solution (Friday Feb. 12, 2010)
  ArrayComm and CEVA today announced an agreement to work toward the implementation of ArrayComm’s full LTE eNodeB PHY on the CEVA-XC™ DSP core. This will provide SoC product developers with a pre-optimized PHY software/processor package to incorporate in their overall system design.
  
  
• Blue Wonder Communications Uses 4M Wireless LTE Protocol Stack to Complete LTE Reference Platform (Friday Feb. 12, 2010)
  Blue Wonder has integrated its LTE baseband solution with the 4M Wireless LTE protocol as part of a complete LTE terminal reference platform.
  
  
• Silicon Hive announces World's First Programmable Digital Radio Frequency Processor for Smart Phones (Thursday Feb. 11, 2010)
  Silicon Hive announces HiveFlex CSP2500 Digital RF Processor. The silicon-proven CSP2500 processor enables fully C-programmable, multi-standard smart phone transceiver platforms targeting EDGE, UMTS, LTE, cdma2000, WiFi and WiMAX technologies.
  
  
• Eureka Technology Supports PLB Bus Interface for Most of Its Popular IP Cores (Thursday Feb. 11, 2010)
  Eureka Technology today announces the availability of the CoreConnect™ PLB™ Bus interface option for most of its IP core products. PLB Bus is the native interface standard for PowerPC and Power Architecture-based embedded processors and the Xilinx MicroBlaze™ CPU. By supporting the PLB™ bus interface standard, Eureka’s IP cores can be integrated seamlessly with any SoC design based on these standard CPU cores.
  
  
• Athena Delivers Powerful 3GPP LTE Multi Radix FFT Processor Core (Wednesday Feb. 10, 2010)
  The Athena Group today announced the general availability of its multi-radix FFT core for LTE and other OFDM-based wireless communications. The PFFT-M for LTE delivers the throughput needed for basestation LTE downlink OFDMA as well as the flexibility to handle the complexity of LTE uplink SC-FDMA in a single core.
  
  
• IPextreme and Globetech Solutions Announce Availability of Industry's First Complete IEEE 1149.7 cJTAG IP Solution (Wednesday Feb. 10, 2010)
  IPextreme and Globetech Solutions today announced the availability of the electronics industry's first complete IEEE 1149.7 cJTAG IP solution. The solution, comprising IPextreme's cJTAG silicon IP (SIP) and Globetech's cJTAG verification IP (VIP) products, will help system designers quickly and easily take advantage of the many performance and cost saving features of the 1149.7 standard.
  
  
• Imec and Holst Centre present ADC with record figure of merit suited for low energy radios (Wednesday Feb. 10, 2010)
  Imec and Holst Centre report an ultra-low power 8 bit analog to digital convertor (ADC) consuming only 30fJ energy per conversion step. This world-class figure of merit ADC is especially suited for upcoming low energy radios in the ISM (industrial, scientific and medical) radio bands such as low-energy Bluetooth or IEEE 802.15.6 for body-area networks.
  
  
• Imec, Renesas and M4S report a single-chip reconfigurable multi-standard wireless transceiver in 40nm CMOS (Wednesday Feb. 10, 2010)
  The fully reconfigurable transceiver is compatible with various wireless standards and applications, including the upcoming mobile broadband 3GPP-LTE standard.
  
  
• Rambus Unveils Mobile XDR Memory for Next-Generation Mobile Products (Monday Feb. 08, 2010)
  Rambus today unveiled its Mobile XDR(TM) memory architecture for next-generation mobile products. Mobile XDR memory offers a high-bandwidth, low-power memory architecture to enable devices that exceed the power and performance targets for next-generation mobile products.
  
  
• Tensilica Introduces Second Generation ConnX BaseBand Engine DSP for Demanding Algorithms for LTE/4G Wireless Handsets and Base Stations (Monday Feb. 08, 2010)
  Tensilica today introduced ConnX BBE16, its second generation baseband engine for LTE (long-term evolution) and 4G baseband SOC (system-on-chip) designs. ConnX BBE16's 16-way MAC (multiply accumulator) architecture is optimized for the most demanding wireless DSP (digital signal processing) tasks, including OFDM (Orthogonal Frequency-Division Multiplexing) algorithms and FFT (Fast Fourier Transform), FIR (Finite Impulse Response), IIR (Infinite Impulse Response), and matrix computation.
  
  
• IP Cores, Inc. Announces a Family of Low-Latency AES/GCM IP Cores Supporting IEEE 802.11ad and WiGig Standards (Thursday Feb. 04, 2010)
  IIP Cores, Inc. Announces a New Low-Latency Family of Silicon IP Cores Supporting the GCM-AES Mode as Defined by the NIST Publication SP800-38D and Used by Wireless Communication Standards IEEE 802.11ad and WiGig. Starting at 64K ASIC Gates and Throughput of 20 Gbps for the Low-End GCM5-32 Core, GCM5 Family of Cores Provides an Efficient Encryption Solution for an SoC Designer that Has to Work with Very Short Communication Data Packets and Multi-Gigabit per Second Data Rates.
  
  
• Blue Wonder Communications Launches LTE-IP Product BWC200 (Thursday Feb. 04, 2010)
  Blue Wonder Communications, the independent design house and licensor of LTE-IP and system solutions, today announced the availability of its embeddable LTE modem IP (Intellectual Property) product BWC200. It constitutes a complete LTE subsystem that can easily be integrated in System-on-Chip (SoC) platforms and consists of a complete physical layer including layer 1 hard- and software.
  
  
• Posedge Announces ONFI-2.2 Compliant Universal Flash Controller IP Core (Thursday Feb. 04, 2010)
  Posedge has announced the availability of Universal Flash Controller (UFC) Soft IP Core that interfaces to NAND, NOR, and Serial Flash devices fully conforming to standards such as the latest Open NAND Flash Interface Working Group (ONFI) 2.2 specification. Posedge has developed a flexible and high performance Universal Flash Controller leveraging its vast experience in Storage and Flash Systems.
  
  
• Cyclic Design Releases Advanced BCH Error Correction IP for Next Generation NAND Flash Applications (Wednesday Feb. 03, 2010)
  Cyclic Design announces advanced BCH ECC, supporting the next generation flash memory devices that require higher levels of error correction codes (ECC). Companies can preserve their investment in existing NAND flash hardware and software solutions by upgrading to this ECC infrastructure.
  
  
• SMSC Launches MediaLB Device Interface Macro IP Supporting 6-Pin MediaLB (Tuesday Feb. 02, 2010)
  SMSC today announced the availability of its OS62420 MediaLB® Device Interface Macro IP including 6-pin support. The macro offers a complete MediaLB device supporting both single-ended MediaLB 3-Pin and additionally the new differential MediaLB 6-Pin interfaces to Media Oriented Systems Transport (MOST®) Intelligent Network Controllers (INICs).
  
  
• MoSys Announces Breakthrough Bandwidth Engine ICs and Serial Chip-to-Chip Communications Interface for Next Generation Networking Applications (Tuesday Feb. 02, 2010)
  MoSys today unveiled a roadmap for its new Bandwidth Engine™ integrated circuit (IC), which will combine MoSys' patented 1T-SRAM® high-density embedded memory with its ultra high-speed 10 Gigabits per second (Gbps) SerDes interface (I/O) technology and an arithmetic logic unit (ALU).
  
  
• Innopower Offers Industrial-leading Miniaturized Cell Library, the miniLib+ and miniIO+, in 130nm, 110nm, 65nm and 55nm Technologies (Tuesday Feb. 02, 2010)
  Innopower Technology, a wholly owned subsidiary of Faraday Technology, announced today the availability of the industrial-leading miniaturized cell libraries, miniLib+™ and miniIO+™, in 130nm, 110nm, 65nm and 55nm Technologies.
  
  
• Arasan Chip Systems offers a complete line of Memory Card Controller IP Cores and Software stacks (Tuesday Feb. 02, 2010)
  Arasan announced today the availability of a complete portfolio of Memory Card Controller IP cores and corresponding software stacks. These card controller IP support the highest performance card formats: Secure Digital (SD / SDIO 3.0), Multimedia Card (e.MMC 4.4), Memory Stick (MSPro, MSPro-Duo), CompactFlash (CF+) and Picture Card (xD) card formats.
  
  
• IP Cores, Inc. Announces an Update of its Elliptic Curve Crypto Accelerator (Tuesday Feb. 02, 2010)
  IP Cores, Inc. Announces an Update of the ECC1 Elliptic Curve Cryptography (ECC) Accelerator that Simplifies the ECDH and ECDSA firmware implementation.
  
  
• Tensilica Introduces HiFi EP DSP Core for High Quality Audio in Home Entertainment and Smartphone Applications (Monday Feb. 01, 2010)
  Tensilica today introduced HiFi EP, a superset of the HiFi 2 architecture that is optimized for simultaneous multichannel codec support and/or continuously expanding audio pre and post processing in home entertainment products such as Blu-ray Disc players, digital television (DTV), and Smartphones. It has also been enhanced for very efficient, high-quality voice pre-and post-processing.
  
  
• Chips&Media to Demonstrate Latest IP at Mobile World Congress 2010 (Monday Feb. 01, 2010)
  Chips&Media today announced that it will show off its advanced decoder and encoder IP cores, Coda851 and Chips&Media-powered end products at Mobile World Congress 2010.
  
  
• Dolphin Integration announces the availability of a complete FREE evaluation kit for its Memory CACHE controller (Friday Jan. 29, 2010)
  Dolphin Integration announces the availability of a complete FREE evaluation kit for its Memory CACHE controller. Its name I-Stratus-LP stands for its position at level L1 as Instruction Cache for any processor in search for Low-Power.
  
  
• Aeroflex Gaisler Announces the Next Generation Leon Processor (Wednesday Jan. 27, 2010)
  Aeroflex Gaisler today announced the next generation LEON processor - the LEON4, providing the industry a high performing, licensable 32-bit processor core based on the SPARC V8 architecture. The LEON4 complements the widely used LEON3 processor for high-performance embedded applications across a broad spectrum of demanding consumer and industrial applications.
  
  
• Dolphin Integration: the embedded audio CODEC with smallest power consumption on the market (Monday Jan. 25, 2010)
  The Helium architecture, already successfully implemented by Dolphin Integration in 130 nm G audio CODECs, is now adapted to the 180 nm and its shrunk versions at 160 nm and 152 nm. Specifically suited for portable applications requiring the longest playback capability, Helium components are cost-optimized both through silicon area and through lowest Bill-of-Material.
  
  
• Synopsys Expands DesignWare IP Portfolio with MIPI IP Solutions (Monday Jan. 25, 2010)
  Synopsys today announced the addition of silicon-proven DesignWare® MIPI IP consisting of 3G DigRF Controllers and PHY, Camera Serial Interface 2 (CSI-2) Host Controller and D-PHY to its IP portfolio.