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IP / SOC Products News

• TAKUMI Starts Licensing New Graphics Accelerator IP cores supporting 2D Vector Graphics (Monday May. 11, 2009)
  TAKUMI announced today that the company has started licensing GV500 and GV300, TAKUMI’s new graphics accelerator IP core supporting 2D Vector Graphics for use mainly in mobile phones and digital consumer electronics products. Both IP cores support the API standards for embedded systems: GV500 supports both OpenGL ES1.1 and OpenVG1.1 while GV300 supports OpenVG1.1.
  
  
• CEVA Partners with SMIC to Deliver Fully Functional Silicon for CEVA-TeakLite-III DSP Core (Monday May. 11, 2009)
  CEVA today announced the availability of fully-functional silicon for the 32-bit CEVA-TeakLite-III DSP core. The first chips were produced on SMIC's 90nm process and exceeded 600MHz.
  
  
• Qualcore initiates standard cell library development-new business wing (Thursday May. 07, 2009)
  QualCore Logic, an intellectual property (IP) and full-service, mixed-signal application specific integrated circuit (ASIC) realization company today announced that it added Standard cell library development as its new business wing.
  
  
• Achronix Taps Signali for 10/40/100Gbps Encryption IP in World's Fastest FPGAS (Thursday May. 07, 2009)
  Achronix Semiconductor, maker of the world's fastest field-programmable gate arrays (FPGAs), today announced the availability of new, high-performance Advanced Encryption Standard (AES) IP cores for its Speedster(TM) 1.5 GHz family.
  
  
• Sonics Answers Challenge of Designing Embedded SoCs Containing Multiple IP Blocks (Tuesday May. 05, 2009)
  Sonics has announced the Sonics Network for AMBA® Protocol or SNAP™. The product is a cost-effective, turn-key solution designed to simplify the on-chip bus design for complex embedded SoCs by turning multilayer bus designs into an IP block.
  
  
• DOLPHIN Integration Announces High Density BTF Library at 65 nm (Monday May. 04, 2009)
  Dolphin Integration extends at 65 nm the ultra High Density design of the “SESAME HD BTF” library, celebrated as the densest library on the market even before the advent of Back-Tracking Freedom (BTF).
  
  
• Passing the Compliance Test, Faraday Launch PCIe2.0 at 90nm (Tuesday Apr. 28, 2009)
  Faraday today announced that their PCIe GenII PHY, developed based on the PCI Express 2.0 specification, has passed PCI-SIG® APAC compliance test in April. This PHY is designed for UMC 90nm process and now available for ASIC customers.
  
  
• Digital Core Design Announces World's smallest and fastest 8051 Core (Friday Apr. 24, 2009)
  DCD releases World's smallest and fastest 8051 core. The 7150 ASIC gates for complete system including 8051-CPU, full duplex UART, Timers 0&1, Advanced Power Management Unit, eight I/O lines, eight external interrupts INT0-INT7 and 2-wire DoCD on-chip debugger is the best achievement on the IP Market. DT8051 runs Dhrystone 2.1 benchmark program 8.1 times faster than the original 80C51 at the same frequency.
  
  
• HDL Design House announces high performance AHB SPI flash memory controller (HIP 3100) (Wednesday Apr. 22, 2009)
  HDL Design House announces HIP 3100, a high performance AHB SPI flash memory controller. The SPI controller (HIP 3100) offloads AHB master and software from direct control of data transfers to/from flash memory subsystem, generation of SPI memory control signals, and increases overall memory subsystem performances.
  
  
• Sidense OTP Memory IP Enables 65nm Mobile Handset Chip (Tuesday Apr. 21, 2009)
  idense, a leading developer of Logic Non-Volatile Memory (LNVM) IP cores, today announced that its 1T-OTP one-time programmable (OTP) memory IP is available for customer designs at the 65nm process node. Sidense is the first embedded OTP vendor to announce high density (above 1 Mbit) product availability for both standard-logic and low-power 65nm implementation.
  
  
• Denali Software and Prism Circuits Prove DDR3 Controller-PHY Interoperability (Tuesday Apr. 21, 2009)
  Prism Circuits and Denali Software today announced interoperability validation of Prism's DDR3/2 Combo PHY with Denali's Databahn Memory Controller. Prism's fully-integrated solution complies with the latest DFI specification and provides the physical layer (PHY) interface between the controller logic and DDR3 DRAM devices to achieve datarates up to 2133Mbps.
  
  
• Kilopass Technology Expands Embedded Non-Volatile Memory Offering To Address Mobile, Consumer, and Computing Markets (Monday Apr. 20, 2009)
  Kilopass announced today BriteXPM, a new product family of one-time programmable (OTP) embedded non-volatile memory (NVM) for mobile, consumer and computing applications requiring faster random access time. As much as 40% improvement in random access time is achieved from the industrial and automotive product lines.
  
  
• TSMC/GUC 65LP ARM 1176JZF hardened cores Open Doors for 65nm Designers (Monday Apr. 20, 2009)
  TSMC and GUC today jointly announced that they have successfully implemented and obtained silicon samples of a high speed ARM 1176 core on TSMC’s 65 LP process, and an ultra low power ARM 1176 core which has been validated in GUC’s low power design platform. The first of the new developments is an ARM 1176JZF core capable of operation up to 1.10 GHz.
  
  
• ARM Announces Availability of Industry's Broadest 40nm G Physical IP Platform (Monday Apr. 20, 2009)
  ARM today announced the availability of the industry’s most comprehensive IP platform for TSMC’s 40nm G manufacturing process. This latest silicon-validated physical IP from ARM enables cost-effective development of performance driven consumer devices requiring advanced functionality without increasing power consumption.
  
  
• Vanguard Software Solutions Releases IP Cores for Panasonic AVC-Intra and H.264 CABAC; Transcoding Solutions for Video (Monday Apr. 20, 2009)
  Vanguard Software Solutions will showcase its latest H.264 technology at NAB 2009 trade show in Las Vegas, NV. Included are: support for Panasonic AVC-Intra and H.264 CABAC IP Cores for FPGA and custom ASICs; Real-Time AVC TRANSCODING required in Internet/Web Video Casting and H.264 SVC support required in video communications markets.
  
  
• CoreEL Technologies Creates Broadcast & Professional Video Grade H.264 High Profile Decoder Solution (Monday Apr. 20, 2009)
  CoreEL Technologies today announced the availability of the H.264 High Profile Decoder IP solution on Xilinx® Virtex® FPGAs, targeted for Professional decoder & Broadcast infrastructure markets. With a maximum resolution support of 1920x1080 (FullHD) at 60 frames per second, the IP introduces a new level of performance and functionality. The H.264 HP decoder supports 4:2:0, 4:2:2 and 4:4:4 chroma formats with programmable bit depth from 8-bit to 12-bits.
  
  
• Arasan Chip Systems Releases MIPI UniPro(sm) Software Stack Extending Its Total IP Solution (Thursday Apr. 16, 2009)
  Arasan announced the immediate availability of the Mobile Industry Processor Interface (MIPI(r)) UniPro Software Stack, a layered, kernel-level stack that eases the integration of UniPro into mobile platforms.
  
  
• IP Cores, Inc. Announces an Ultracompact Version of the Snow 3G Cipher for 3GPP LTE (Thursday Apr. 16, 2009)
  IP Cores, Inc. has announced availability of a version of the SNOW 3G cipher core with very low gate count and power consumption. Along with the ultracompact AES cipher, this cores can be used in the new mobile communication devices for 3GPP LTE networks.
  
  
• PLDA Announces Industry's First SuperSpeed USB Host Bus Adapter Development Platform (Thursday Apr. 16, 2009)
  PLDA today announced that it has begun shipping the first SuperSpeed USB Host Bus Adapter (HBA) development platform. This HBA platform will enable leading-edge companies to develop and test USB 3.0 semiconductor designs or USB 3.0 software stacks more easily and efficiently, helping get them to market quicker.
  
  
• IP Cores, Inc. Announces a New Compact Version of the Elliptic Curve Crypto Accelerator (Thursday Apr. 16, 2009)
  IP Cores, Inc. had designed the ECC1 core that implements the necessary crypto functionality of the ECC algorithm (point multiplication and point verification functionality) and weighs in at less than 10,000 ASIC gates, 630 slices on Xilinx Virtex-5 devices, 2065 LE in Altera Cyclone II, 1137 ALUT in Altera Stratix II, and 7790 tiles for Actel ProASIC3.
  
  
• Synopsys Introduces Lower Power, High-Performance Architecture for AMBA 3 AXI On-Chip Interconnect (Wednesday Apr. 15, 2009)
  Synopsys today announced that it has enhanced its DesignWare® IP for the ARM® AMBA® 3 AXI™ interconnect with the industry's first hybrid architecture implementation, enabling dedicated high-performance and shared low-performance channels to be combined within a single AMBA 3 AXI on-chip interconnect.
  
  
• Lead Tech Design unveils its brand new range of microcontrollers for embedded applications (Tuesday Apr. 14, 2009)
  Lead Tech Design, which specializes in the design of ASIC/FPGA System-on-Chip (SoCs) and embedded software for Linux and Linux hard real time with Xenomai, is extending its offering with aRDAC, a brand new range of configurable microcontrollers, guaranteeing performance of 1 MIPS/MHz.
  
  
• IP Cores, Inc. Announces Ultracompact Version of Kasumi Cipher for 3G Devices (Tuesday Apr. 14, 2009)
  IP Cores, Inc. has announced availability of a version of the Kasumi cipher with very low gate count and power consumption. Along with the ultracompact AES cipher, this core can be used in the new mobile communication devices for 3G networks.
  
  
• Arasan Chip Systems Extends Its Strategic Mobile Initiative by Offering MIPI UniPro IP Solution (Friday Apr. 10, 2009)
  Arasan announced the immediate availability of the Mobile Industry Processor Interface (MIPI(r)) UniPro Controller IP, a layered, high-speed protocol that provides connectivity between applications processors and wireless, multimedia and mobile chipsets. As a leading provider of mobile IP, Arasan continues to strengthen its Strategic Mobile Initiative by expanding its MIPI IP portfolio with the UniPro IP.
  
  
• Dolphin Integration launches new microcontroller configurations (Friday Apr. 10, 2009)
  Dolphin Integration launches new microcontroller configurations and bundles of the i80251 legacy for best density and lowest power consumption.
  
  
• On2 Technologies Introduces Hantro 9170 HD Video Decoder (Friday Apr. 10, 2009)
  On2 today announced the availability of its ninth-generation hardware video codec design, the Hantro 9170. The design supports video playback up to full HD (1080p) resolution at 60 frames per second (fps) in multiple formats including MPEG-1, MPEG-2, MPEG-4, Sorenson Spark(R), H.263, H.264, VC-1 and REALVIDEO(R) 8, 9 & 10, as well as up to 66 megapixel JPEG still images.
  
  
• intoPIX enhances its multichannel JPEG 2000 codec IP-Cores to meet broadcasters' needs for live events (Wednesday Apr. 08, 2009)
  intoPIX presents its latest IPX-JPHD encoders and decoders for the broadcast industry. This new release not only delivers all the benefits of JPEG 2000, but is now able to provide the highest quality images for live events while meeting the tight latency requirements required to deliver this type of content.
  
  
• DCD Announces the 5th generation of World's fastest and most popular 8051 IP Core (Tuesday Apr. 07, 2009)
  Digital Core Design (DCD) today releases the 5th generation of World's fastest and most popular 8051 core. DP8051 runs Dhrystone 2.1 benchmark program 11.45 to 14.74 times faster than the original 80C51 at the same frequency.
  
  
• Gennum's Snowbush IP Group Enables Rapid Deployment of SATA and SAS 6 Gb/s Products (Monday Apr. 06, 2009)
  Gennum today announced that its Snowbush IP group has developed a SATA 6 gigabits per second (Gb/s) physical layer (PHY) IP block. The new IP also satisfies the stringent requirements of the latest Serial Attached SCSI (SAS) standard, SAS 2.0 (SAS-2). The SATA/SAS IP is being offered for manufacture in a variety of 65-nm and 45-/40-nm processes, including TSMC, as well as Common Platform Alliance members IBM, Chartered and Samsung.
  
  
• LogicVision Delivers New Embedded Boundary Scan Core Reuse Capability (Thursday Apr. 02, 2009)
  With new cores increasingly containing chip I/O circuitry and pads, LogicVision's new embedded boundary scan solution allows needed I/O DFT structures to be added directly into these cores rather than later at the top level during full chip integration.