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IP / SOC Products News

• Denali Software First to Ship PCI Express 3.0 Controller IP Cores (Tuesday Mar. 31, 2009)
  Denali today announced availability and first customer shipments of the latest Denali Databahn(TM) controller IP cores, based on the current preliminary version of the PCI Express® (PCIe) 3.0 specification, for use in next-generation chip designs.
  
  
• Sonics Memory Scheduler Improves Memory Efficiencies in High-Bandwidth SoCs (Tuesday Mar. 31, 2009)
  Sonics has announced the availability of the MemMax Memory Scheduler 3.0, a DRAM access scheduler ideally designed for use with DDR2 and DDR3. geted at SoCs requiring high-bandwidth traffic management to the memory subsystem, the new MemMax Scheduler accelerates on-chip performance while easing design integration.
  
  
• Cambridge Consultants demonstrates Centaur GSM PHY reference design IP (Monday Mar. 30, 2009)
  Cambridge Consultants is demonstrating Centaur, a comprehensive GSM/GPRS/EDGE/E-EDGE physical layer (PHY) reference design. The novel reference design enables the development of advanced cellular base-stations and femtocells that incorporate 2G and 2.75G capability, addressing the ultra low-cost, mass-market and integration requirements of the developing world.
  
  
• Dolphin Integration Announces Memory Compiler Haumea at 65 nm (Friday Mar. 27, 2009)
  This generation of Haumea addresses the 65 nm LP process with compilers for both RAM and ROM.
  
  
• Arasan Chip Systems announces the World's First 75-in-1 Multi-Card Controller IP (Thursday Mar. 26, 2009)
  Building upon its leadership position in Secure Digital (SD/SDIO) solutions, Arasan has introduced yet another first – the 75-in-1 Multi-Card Controller. The family of controller IPs natively supports popular memory and I/O formats including SD, eSD, SDIO, MMC, eMMC, MS, MS Pro, CF and xD and their derivatives.
  
  
• MAZeT offers EnDat-IP for customized applications (Wednesday Mar. 25, 2009)
  MAZeT GmbH offers the IP core certified by the originator for the EnDat master (Heidenhain company) for implementation in FPGAs and ASICs. The serial communication interface for rotary and linear distance measuring systems was developed by MAZeT and maintained as product.
  
  
• Sarance Technologies Releases 40G/100G Ethernet IP for General Availability (Friday Mar. 20, 2009)
  Sarance Technologies announced today the immediate availability of HSEC (High Speed Ethernet Core), the world’s first commercially available Media Access Controller (MAC), Physical Coding Sublayer (PCS), and Multi Lane Distribution (MLD) IP conforming to the emerging 40Gigabit Ethernet (40GE) and 100Gigabit Ethernet (100GE) standard.
  
  
• MAZeT offers Interbus-IP for customized FPGA and ASIC implementation (Thursday Mar. 19, 2009)
  MAZeT GmbH offers IP cores for the Interbus protocol (SUPI4 / Phoenix Contact) for implementation in FPGAs and ASICs. The protocol chip for serial communication interfaces in automation technology was developed and maintained by MAZeT.
  
  
• MIPS Technologies Achieves Technical Milestones for USB 2.0 High-Speed PHY IP (Wednesday Mar. 18, 2009)
  MIPS Technologies today announced that its 40nm USB 2.0 High-Speed PHY IP achieved certification from the USB Implementers Forum (USB-IF) and met TSMC’s TSMC9000 standards in its 40nm LP process.
  
  
• Faraday Offers 0.13um miniIO with around 40% Area-Saving and Robust ESD Performance (Wednesday Mar. 18, 2009)
  Faraday today announced the availability of its innovative IO offering at 0.13um, miniIO™. Compared with general IO pads, the advantage of Faraday's miniIO™ is its area reduction, up to 40% for a pad-limit design with 200 pins, and still keeping the same programming IO functionality, while achieving robust ESD performance.
  
  
• Imagination Technologies launches advanced, highly-efficient POWERVR SGX543MP multi-processor graphics IP family (Monday Mar. 16, 2009)
  Imagination Technologies announces further details of the first POWERVR SGX graphics IP core with multi-processor (MP) core support. The technology, henceforth POWERVR SGX543MP, is being delivered to customers in SGXMP2 (two-core) to SGXMP16 (16-core) variants.
  
  
• Silistix Announces Industry's First Mixed Synchronous/Asynchronous Network-on-Chip Solution in CHAIN(R)works 3.0 (Monday Mar. 16, 2009)
  Silistix Inc. today announced CHAINworks 3.0, enabling architects and designers of complex chips to synthesize Networks-on-Chip (NoC) using both synchronous and asynchronous circuit techniques.
  
  
• Full debugging features at the lowest silicon cost with Dolphin Integration 16-bit microcontroller thanks to the innovative Virtual Clone (Friday Mar. 13, 2009)
  Offering to 8051 software developers a complete set of debugging features - unlimited watchpoints, unlimited breakpoints, unlimited trace memory depth, etc - at practically no silicon expense is achievable with the patented solution of Virtual Clone.
  
  
• Evatronix Releases High Resolution Display Controller IP Core (Tuesday Mar. 10, 2009)
  Evatronix announced today the release of DISPLAY-CTRL – a High Resolution Display Controller IP core for PC, home video, mobile and industrial applications. The controller supports all common display formats, from QVGA to WUXGA and Full HD resolutions.
  
  
• CebaTech Takes Intellectual Property Business to the Next Level with CebaRIP Rapidly Tunable Cores (Tuesday Mar. 10, 2009)
  CebaTech has announced that it is taking its IP business to the next level with a library of rapidly tunable IP cores, CebaRIP cores. The initial offering is targeted at the IP realization of standard algorithms used extensively in storage, storage area network (SAN), network-attached storage (NAS), and networking applications, including compression, encryption, fingerprinting, and more. In addition to these standard CebaRIP cores,
  
  
• Synopsys DesignWare USB 2.0 nanoPHY and PCI Express 1.1 PHY IP First to Achieve Compliance in UMC's 65-Nanometer Process Technologies (Tuesday Mar. 10, 2009)
  Synopsys, Inc. , a world leader in software and IP for semiconductor design and manufacturing, today announced that the DesignWare® USB 2.0 nanoPHY IP and PCI Express® 1.1 PHY are the first IP cores to achieve compliance in UMC's 65-nanometer (nm) SP and LL process technologies.
  
  
• LogicVision Announces Memory BIST & Repair Solutions for 45nm SOI Foundry Customers (Tuesday Mar. 10, 2009)
  LogicVision today announced that IBM has included LogicVision's ETMemory(TM) memory BIST and on-chip self-repair solution for embedded memory test and yield improvement within its advanced 45nm silicon-on-insulator (SOI) semiconductor foundry flow.
  
  
• Gennum's Snowbush IP Group Enables Proliferation of PCI Express Gen 2 Products With Industry's First 9-Port Switch IP Block (Monday Mar. 09, 2009)
  Enabling the rapid development of multi-port PCI Express (PCIe) SoCs optimized for a variety of applications and price points, Gennum today announced that its Snowbush IP group has developed a PCIe Gen 2 9-port switch IP block with optional embedded endpoints.
  
  
• Gennum's Snowbush IP Group Delivers Industry's First Available USB 3.0 Integrated PHY and Controller IP (Monday Mar. 09, 2009)
  The integrated Snowbush device PHY and controller solution satisfies the 5 Gb/s speed requirement of USB 3.0, and exceeds the critical specifications for jitter and jitter tolerance, providing substantial margin to designers for creating robust products with excellent interoperability.
  
  
• Intelop announces 10 G bit Ethernet MAC + PCIe + AMBA 2.0 Core which Receives and Transmits 64 - 1518 Byte packets at full line rate and is customizable for implementing differentiated application features (Monday Mar. 09, 2009)
  The 10-Gbit Ethernet MAC is being delivered for FPGA designs and for ASIC designs. A separate verification suite was developed by intelop for targeting this core to ASIC design flows as well. The PCIe or AMBA interfaces can easily be removed for design applications that do not require them.
  
  
• Dolphin Integration announces New High Density library Back-Tracking-Free in 180 and 65 nm (Friday Mar. 06, 2009)
  Dolphin Integration pursues its unique strategy in the field of standard cells with their unique "Reduced Cell Stem Libraries" by enhancing its celebrated ultra High Density library “SESAME uHD” with the patented Back Tracking Freedom (BTF).
  
  
• Alvand Technologies Announces Industry's Lowest Power, Smallest Die-Area Analog-to-Digital Converter (ADC) Intellectual Property (IP) Solution in Advanced 65nm Process Node (Thursday Mar. 05, 2009)
  Designed in UMC’s leading 65nm manufacturing process node, the ALVADC10_205M65U IP solution from Alvand is a robust 10-bit, 205 Mega-samples-per-second (MSPS) pipeline ADC that features excellent dynamic range performance, with a signal-to-noise ratio (SNR) of 58.5 dBFS, and high immunity to substrate noise.
  
  
• Synopsys DesignWare IP for PCI Express First IP to Pass Agilent Technologies' Inline Error Injection Testing (Thursday Mar. 05, 2009)
  Synopsys today announced its DesignWare® controller and PHY IP for PCI Express 2.0 and 1.1 has passed Agilent Technologies' inline error injection testing utilizing Agilent's PCI Express Jammer tool.
  
  
• NXP Semiconductors and MIPS Technologies Introduce Industry's First 45nm HDMI 1.3 Receiver IP Solution (Tuesday Mar. 03, 2009)
  MIPS Technologies today announced that its cooperation with NXP Semiconductors has resulted in the industry’s first 45nm HDMI 1.3 receiver IP solution. Created through a combination of co-development and co-licensing, the HDMI receiver IP is integrated in NXP’s global digital TV solution: TV550 platform, and is available for license as IP from MIPS Technologies.
  
  
• MIPS Technologies Continues to Drive HDMI into Portable Applications with 40nm Interface IP (Tuesday Mar. 03, 2009)
  MIPS Technologies today announced it is continuing to drive HDMI into portable electronic devices with new IP that is optimized for ultra-low power SoC implementation. With its new 40nm HDMI 1.3 Interface IP (Controller + PHY), MIPS continues to extend its leadership in the digital home, enabling HDMI content to go mobile.
  
  
• Intelop announces customization services for their TCP-Offload Engine SoC IP for customers to target specific protocol implementation or differentiated features (Monday Mar. 02, 2009)
  Intelop today announced addition of value added customization services to their TCP offload engine SoC solutions that are integrated with ARP hardware module, G Bit Ethernet MAC and AMBA 2.0 bus interfaces running at 2 Gbps sustained rates.
  
  
• LogicVision Extends Built-In Self-Test Products to be Directly Controllable From Embedded CPU Cores, Easing System Test and Maintenance (Thursday Feb. 26, 2009)
  LogicVision today announced that it has developed new technology that will enable easy access to chip level BIST capabilities for board and system-level test and maintenance activities. All of the advanced test and diagnostic functions used during device manufacturing test can now be made available to virtually any embedded CPU core or controlled from any external CPU bus such as I2C, allowing these embedded capabilities to be leveraged by system maintenance functions.
  
  
• Synopsys Enhances DesignWare DDR PHY IP with Service to Verify Signal Integrity (Wednesday Feb. 25, 2009)
  The DesignWare® DDR PHY signal integrity service examines the entire memory subsystem extending far beyond the DDR PHY to help ensure the robustness of the electrical signaling within the system. If necessary, the service offers recommendations for improved performance.
  
  
• Intelop announces major enhancements to their TCP-Offload Engine SoC IP that has integrated GEMAC, ARP module and AMBA 2.0 bus and PCIe interface running at 2-Gbps also is capable of managing thousands of simultaneous TCP sessions in realtime (Monday Feb. 23, 2009)
  Intelop today announced major enhancements to their second generation TCP offload engine SoC solution integrated with ARP hardware module, G Bit Ethernet MAC and AMBA 2.0 bus interface running at 2 Gbps sustained rates.
  
  
• ARM Launches Its Smallest, Lowest Power, Most Energy Efficient Processor (Monday Feb. 23, 2009)
  ARM today announced the ARM® Cortex™-M0 processor, the smallest, lowest power and most energy-efficient ARM processor available. The Cortex-M0 processor, which consumes as little as 85 microwatts/MHz (0.085 milliwatts) in an area of under 12K gates when using the ARM 180ULL cell library, builds on the unrivaled expertise of ARM as a leader in low-power technology and a key enabler for the creation of ultra low-power devices.