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IP / SOC Products News

• LogicVision Extends Built-In Self-Test Products to be Directly Controllable From Embedded CPU Cores, Easing System Test and Maintenance (Thursday Feb. 26, 2009)
  LogicVision today announced that it has developed new technology that will enable easy access to chip level BIST capabilities for board and system-level test and maintenance activities. All of the advanced test and diagnostic functions used during device manufacturing test can now be made available to virtually any embedded CPU core or controlled from any external CPU bus such as I2C, allowing these embedded capabilities to be leveraged by system maintenance functions.
  
  
• Synopsys Enhances DesignWare DDR PHY IP with Service to Verify Signal Integrity (Wednesday Feb. 25, 2009)
  The DesignWare® DDR PHY signal integrity service examines the entire memory subsystem extending far beyond the DDR PHY to help ensure the robustness of the electrical signaling within the system. If necessary, the service offers recommendations for improved performance.
  
  
• Intelop announces major enhancements to their TCP-Offload Engine SoC IP that has integrated GEMAC, ARP module and AMBA 2.0 bus and PCIe interface running at 2-Gbps also is capable of managing thousands of simultaneous TCP sessions in realtime (Monday Feb. 23, 2009)
  Intelop today announced major enhancements to their second generation TCP offload engine SoC solution integrated with ARP hardware module, G Bit Ethernet MAC and AMBA 2.0 bus interface running at 2 Gbps sustained rates.
  
  
• ARM Launches Its Smallest, Lowest Power, Most Energy Efficient Processor (Monday Feb. 23, 2009)
  ARM today announced the ARM® Cortex™-M0 processor, the smallest, lowest power and most energy-efficient ARM processor available. The Cortex-M0 processor, which consumes as little as 85 microwatts/MHz (0.085 milliwatts) in an area of under 12K gates when using the ARM 180ULL cell library, builds on the unrivaled expertise of ARM as a leader in low-power technology and a key enabler for the creation of ultra low-power devices.
  
  
• Innovative Logic announces USB3.0 Device Controller IP (Thursday Feb. 19, 2009)
  Innovative Logic announced today the first release of USB 3.0 Device Controller IP. Inno-Logic's USB3.0 IP offering includes implementation IP as well as verification IP by making use of industry standard latest tools and methodologies.
  
  
• Independent BDTI Benchmarks Recognize CEVA-TeakLite-III as Most Area Efficient and Energy Efficient of all Processors in Its Class (Wednesday Feb. 18, 2009)
  CEVA announced today that BDTI has published certified results for the 32-bit CEVA-TeakLite-III DSP core on its BDTI DSP Kernel Benchmarks™. The CEVA-TeakLite-III achieved highest DSP Area Efficiency and highest DSP Energy Efficiency of all processors in its class certified by BDTI using this benchmark suite.
  
  
• RAD3 Communications Announces Wireless Communications IP Library (Tuesday Feb. 17, 2009)
  RAD3’s wireless solutions consist of: Software Defined Radio and ASIC/FPGA modules targeted to WiMax and LTE; Forward Error Correction modules targeting multiple wireless standards including WiMax, WiFi, LTE and Wireless USB; Industry leading, silicon proven, FFT/IFFT modules
  
  
• Imagination Technologies announces OpenVG 1.1 conformance for POWERVR SGX range of scalable graphics cores (Tuesday Feb. 17, 2009)
  Imagination Technologies reports that its POWERVR SGX520, SGX530 and SGX535 graphics cores have passed the Khronos™ conformance tests for OpenVG 1.1. The cores, which range from SGX520, the world's smallest OpenGL ES 2.0 conformant core, through to high performance OpenGL ES and DirectX solutions, lead the market in delivering shader and vector graphics processing for mobile and embedded devices.
  
  
• Imagination delivers HD H.264 High Profile capability in latest video encoder IP cores (Monday Feb. 16, 2009)
  Imagination Technologies announces two new IP cores in the POWERVR VXE video encoder family. POWERVR VXE320 and VXE360, part of the third generation of Imagination’s video IP family, deliver multi-standard encode, including H.264 High Profile (HP), at SD and HD resolutions respectively.
  
  
• On2 Technologies Announces the Hantro 8270 Area and Speed Optimized 1080p Hardware Video Encoder (Monday Feb. 16, 2009)
  On2 Technologies announced today the introduction of its latest hardware design, the Hantro(TM) 8270 1080p Encoder. The new design supports H.264 Baseline, Main and High Profile video along with 16Mpixel JPEG still images. With a minimal clock frequency requirement, less than 250MHz needed for 30fps 1080p video, the Hantro 8270 is highly suited for low powered chipsets typically used in battery operated devices and consumer electronics.
  
  
• ARM Extends Performance, Size and Power Efficiency Leadership with the First Cortex Processor on 32nm Process (Monday Feb. 16, 2009)
  ARM today announced that the world’s first ARM processor produced on 32nm High-K Metal Gate (HKMG) process technology will be shown at Mobile World Congress, Barcelona. It is the first ever 32nm Cortex™ family processor core, built with ARM Physical IP, on a test chip from the IBM Common Platform in its 32nm High-K metal gate (HKMG) process.
  
  
• ARM NEON Technology to Help Enable Deployment of Dolby Mobile Technology (Monday Feb. 16, 2009)
  ARM today announced that Dolby® Mobile, which enhances the listening experience on mobile phones and portable media players, is now available with ARM® NEON™ technology. NEON technology is a 128-bit SIMD (Single Instruction, Multiple Data) architecture extension for the ARM Cortex-A series family of processors.
  
  
• Imagination announces first member of new vector graphics IP core family (Monday Feb. 16, 2009)
  Imagination Technologies today announced the first in a new family of scalable vector graphics processor IP cores - the POWERVR VGX150.
  
  
• Intelop announces major enhancements to their TCP-Offload Engine SoC IP that also has integrated GEMAC, ARP module and AMBA 2.0 bus and PCIe interface running at 2-Gbps capable of managing thousands of simultaneous TCP sessions (Monday Feb. 16, 2009)
  Intelop today announced major enhancements to their second generation TCP offload engine SoC solution integrated with ARP hardware module, G Bit Ethernet MAC and AMBA 2.0 bus interface running at 2 Gbps sustained rates.
  
  
• Eureka Technology and Dolphin Technology offer complete DDR2/DDR3 Solution for High Performance SoC/ASIC Designs (Thursday Feb. 12, 2009)
  Eureka Technology and Dolphin Technology today announced a joint offering of a complete and seamless DDR memory interface solution. The combination of Eureka DDR controller and Dolphin physical interface (DDR PHY) transceiver provide chip designers a fully integrated and validated solution for high speed DDR2 and DDR3 memory interface integration.
  
  
• GDT announces H.264 XE silicon IP core (Wednesday Feb. 11, 2009)
  H.264 XE is a highly integrated silicon IP core offering H.264 video compression quality at the lowest possible bit rate. The new IP core is designed specifically for XilinxTM based FPGAs and video platforms. H.264XE’s compatibility with Xilinx’s design flow ensures “plug-and-play” immersion in Xilinx’ EDK platform and implementation in all modern Xilinx FPGA devices.
  
  
• Silicon Image Introduces Industry's First Silicon Implementation of 40-nm Low-Power HDMI Version 1.3 Transmitter Analog IP Core (Wednesday Feb. 11, 2009)
  New Ultra Low-Power IP Core Targets Mobile Products Requiring HDMI(TM) or Mobile High-Definition Link (MHL(TM)) Interconnect to Digital Televisions
  
  
• CEVA Unveils Industry's Highest Performance DSP Architecture for 3.5G/4G Terminals and Infrastructure SoCs (Wednesday Feb. 11, 2009)
  CEVA today unveiled CEVA-XC™ -- the industry's highest performance processor architecture designed and optimized for advanced wireless communications.
  
  
• Mitsubishi Electric Develops High-Speed and Compact IP Core for Processing Graphics in Built-in Display Systems (Wednesday Feb. 11, 2009)
  Mitsubishi Electric announced today that it has developed a high-speed and compact intellectual property (IP) core for graphical user interfaces (GUI), to be used in built-in display systems for operating a variety of equipment.
  
  
• Tensilica Enables New Bluetooth Devices with the SBC Decoder and Encoder on Its HiFi 2 Optimized Audio DSP (Wednesday Feb. 11, 2009)
  Tensilica, Inc. today announced the immediate availability of the Bluetooth sub-band codec (SBC) decoder and encoder for its popular HiFi 2 Audio DSP, which can easily be integrated into system-on-chip (SOC) designs.
  
  
• Fastest 8051 IP core downloadable demo from Evatronix. (Monday Feb. 09, 2009)
  Evatronix today announced immediate download availability for its R8051XC2 microcontroller demo. R8051XC2 is the world’s fastest 8051 IP core, with 12.1 times better performance than original Intel 80C51.
  
  
• Intelop delivers industry's first customizable/scalable multi-port Network Switch + 1G/100 MB EMAC + Motorola CPU interface Silicon IP for industrial automation applications (Monday Feb. 09, 2009)
  Intelop today announced delivery of their second 100M/1G bps Ethernet Switch IP with integrated 1G/100M Ethernet MAC and 32 Bit Motorola CPU interface controller. The pioneering new silicon IP has many customizable features that can be programmed by customers based upon Network topology, network deployments, network traffic utilization.
  
  
• IMEC reports low-cost low-power 60GHz solutions in digital 45nm CMOS (Monday Feb. 09, 2009)
  IMEC presents a 60GHz front-end receive chain, phase-locked loop and power amplifier in 45nm digital CMOS technology. These building blocks pave the way to second-generation 60GHz radios by 2010 which will rely solely on plain CMOS, true one-chip solutions.
  
  
• ARM tips plans for Swift and Sparrow processor cores (Thursday Feb. 05, 2009)
  ARM has disclosed plans for processor cores to be introduced into its Cortex range, codenamed Swift and Sparrow. Swift is a low-cost, low-power follow-on to the Cortex M3 microcontroller and Sparrow is aimed at the real-time applications catered for by the Cortex-R family of cores.
  
  
• Arasan Chip Systems Unveils a Complete USB Solutions' Strategy (Thursday Feb. 05, 2009)
  Upon driving its strategy, Arasan has released its latest USB 3.0 SuperSpeed USB solution. The USB xHCI Host Controller and the Device Controller is optimized for low power consumption to extend battery life for portable and consumer products.
  
  
• Aeroflex Gaisler extends the GRLIB IP library with USB 2.0 Device Controller (Thursday Feb. 05, 2009)
  Aeroflex Gaisler AB announced that a USB 2.0 Device Controller IP (Intellectual Property) core is now available as a part of the GRLIB IP library. The Device Controller is intended for simplifying the implementation of USB functions on AMBA-AHB based systems and supports High- and Full-Speed USB traffic.
  
  
• Digital Core Design Introduces LIN Controller Core (Thursday Feb. 05, 2009)
  The DLIN Master/Slave IP core is fully compatible to Local Interconnect Network (LIN) LIN 1.3 and LIN 2.1 industry standards. DLIN core provides an interface between a microprocessor/microcontroller and LIN bus.
  
  
• Synopsys Expands DesignWare SuperSpeed USB IP Offering With xHCI Host Controller (Wednesday Feb. 04, 2009)
  Synopsys today announced the addition of the DesignWare® SuperSpeed USB xHCI Host Controller to the complete DesignWare SuperSpeed USB (USB 3.0) IP solution consisting of device and host controllers, PHY and verification IP.
  
  
• ChipX Introduces 10-bit and 12-bit ADC IP Cores For Data Monitoring, Data Acquisition and Analog Front-Ends in Application (Wednesday Feb. 04, 2009)
  ChipX today announced the addition of a family of 10-bit and 12-bit Analog to Digital Converters (ADCs) to its extensive line-up of analog and mixed-signal Intellectual Property (IP). The new IP cores include three 10-bit ADCs rated at 40Msps, 100Msps and 160Msps. The family of pipeline ADCs also include three 12-bit ADCs rated at 20Msps, 40Msps and 80Msps.
  
  
• CAST Improves SDIO Host and NAND Flash Memory Controller Cores (Tuesday Feb. 03, 2009)
  The new SDIO and NAND Flash controller cores were developed by long-time CAST partner Evatronix SA in Poland. They are part of CAST’s memory and storage controller IP family, which also includes DDR, DDR2, SDRAM, and ATE/IDE IP cores