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IP / SOC Products News

• Chipidea Achieves Certification for USB High-Speed PHY IP on Chartered’s 90nm and 65nm Customer-ready Technologies (Tuesday Dec. 04, 2007)
  Compliant with the USB 2.0 standard and certified by independent certification authority USB Implementers Forum (USB-IF), Chipidea's USB 2.0 On-The-Go (OTG) PHY cores are part of the industry's broadest portfolio of USB high-speed PHY IP that is silicon-proven and certified in 0.18um, 0.13um, 90nm and 65nm on Chartered's customer-ready foundry solutions.
  
  
• Lattice Partners with Oregano Systems to Introduce IEEE 1588 Industrial Ethernet IP Core (Monday Dec. 03, 2007)
  Oregano has ported their IEEE 1588 IP core for clock synchronization over Ethernet to the LatticeXP™ and LatticeXP2™ FPGA families. This IP core implements a popular IEEE standard that is used for many Industrial Ethernet applications to ensure that the various nodes in a network have synchronized real time clocks.
  
  
• DxO Labs Announces Immediate Availability of DxO IPE, the Industry's First Embedded Image Processing Solution (ISP) for Camera Phones with Built-in Enhanced Depth of Field (EDOF) and Optical Fault Correction (Monday Dec. 03, 2007)
  Available as Silicon IP, DxO IPE solution leverages new generation DxO programmable and configurable SIMD RTL core optimized for on-the-fly image processing.
  
  
• Rambus Unveils Ground-breaking Terabyte Bandwidth Initiative (Wednesday Nov. 28, 2007)
  This technology initiative includes the development of new memory signaling innovations that will facilitate blazing fast data rates of 16Gbps and enable a future memory architecture that can deliver an unprecedented terabyte per second (TB/s) of memory bandwidth (1 terabyte = 1,024 gigabytes) to a single System-on-Chip (SoC)
  
  
• Faraday Introduces The ARMv5 Compliant Ultra Low Power Core -- FA606TE (Tuesday Nov. 27, 2007)
  Faraday today launched the ARM v5 instruction set architecture (ISA) compliant processor - FA606TE, which is an ultra low power 32-bit RISC with the synthesizable and configurable features
  
  
• Synopsys' DesignWare IP Passes Certified Wireless USB Testing From USB-IF (Monday Nov. 26, 2007)
  The DesignWare Wireless USB Device IP is designed to the WiMedia Alliance Ultra-wideband (UWB) Common Radio Platform and includes a WiMedia MAC-PHY interface for interoperability with WiMedia UWB PHYs such as those from Alereon and Realtek
  
  
• Noesis Technologies Announces its Compact Area Parameterizable Reed Solomon Decoder and Encoder IP Core (Monday Nov. 26, 2007)
  The ntRS-HT and ntRS-CA IP cores are highly parameterizable and can be used in a variety of applications such as IEEE 802.16a, IEEE.802.16e, DVB-S, DVB-H, ITU G.984(GPON), ITU G.975, xDSL, IESS-308, CCSDS e.t.c.
  
  
• ARC Introduces the IP Industry's Lowest Power MP3 Solution (Tuesday Nov. 20, 2007)
  ARC International today announced an optimized MP3 decoder for its ARC® Sound Subsystem operating at under 7 MHz and dissipating less than 0.46 mW of power in a TSMC 90 G process.
  
  
• MoSys Introduces SATA II IP for Storage, Network Storage and Connectivity Markets (Friday Nov. 16, 2007)
  The MoSys SATA GEN II (3.0Gbs) PHY IP is compliant with Serial ATA II Electrical Specification Revision 2.5 and is backward compatible to the widely deployed Gen I (1.5GbS) Serial ATA standard.
  
  
• Sonics Extends GALS Support for Advanced Power Management (Thursday Nov. 15, 2007)
  SonicsExpress enables developers to extend the globally asynchronous locally synchronous (GALS) capabilities of Sonics SMART Interconnect solutions, while maintaining automated system level verification and ultra-low power consumption.
  
  
• Innovision launches Gem Near Field Communication IP evaluation and licensing programme (Wednesday Nov. 14, 2007)
  Innovision Research & Technology is making its unique Gem™ Near Field Communication (NFC) semiconductor intellectual property (IP) available under an evaluation licensing programme. This will enable semiconductor companies to develop NFC capability, either for stand-alone solutions or as part of System-on-Chip (SoC) integrated NFC solutions.
  
  
• Phylinks Announces Working-First-Silicon for PHY-820: PCIe PHY with Leading-Edge DFT Features (Wednesday Nov. 14, 2007)
  Phylinks, Inc., an innovator of IP cores for the design of physical layer (PHY) high-speed serial interfaces, announced today that it has delivered working-first-silicon of its PHY-820 PCIe PHY at the .13u process technology node.
  
  
• Chartered, Socle Offer ARM926EJ Development Kit For 65nm Low Power Process (Wednesday Nov. 14, 2007)
  The kit features a hardened ARM926EJ-S core operating at over 500MHz, and provides support for all necessary interfaces, peripherals and software for a feature-rich ARM-based SoC. The ARM926EJ Chartered 65 nm test chip coded as CMPU491A was completed using a comprehensive solution from Chartered Design Enablement portfolio.
  
  
• Altera and Synopsys Collaborate to Make Nios II Processor Core Available for ASIC Designs (Tuesday Nov. 13, 2007)
  Altera Corporation and Synopsys today announced that Altera's popular Nios® II processor core will be available for licensing through Synopsys' DesignWare® Star IP Program.
  
  
• Sidense Achieves Working Embedded OTP at 65nm (Tuesday Nov. 13, 2007)
  Sidense, a leading developer of Logic Non-Volatile Memory (NVM) IP cores, today announced it has successfully achieved functional embedded NVM at 65nm silicon and will complete full qualification in Q1 of 2008. The initial 65nm offering includes standard/general and low power/leakage processes.
  
  
• RF Engines Ltd (RFEL) announces new CORDIC IP design (Tuesday Nov. 13, 2007)
  RFEL has announced the availability of its latest ‘Vector Rotation/Translation’ IP core. This core offers a sub-set of the features provided by the traditional CORDIC algorithm and dependant on the application, delivers significant savings in cost, power and size.
  
  
• ARM Introduces SecurCore SC300 Processor For Smart Card Applications (Tuesday Nov. 13, 2007)
  ARM today announced the availability of the ARM® SecurCore® SC300™ processor, designed specifically for contactless and USB smart cards and embedded security applications.
  
  
• Toshiba Delivers DFI-Compatible DDR PHY to Speed Custom SoC Memory System Designs (Tuesday Nov. 13, 2007)
  Denali Software today announced the availability of DDR PHY interface designs from Toshiba that are compatible with the recently announced DDR-PHY Interface (DFI) version 1.0 specification.
  
  
• Silicon Hive announces HiveFlex VSP 2500 World's first fully-programmable multi-processor solution for Full High Definition (1080p) video codecs (Tuesday Nov. 13, 2007)
  Silicon Hive announces the HiveFlex VSP 2500 Video Signal Processing solution for Full High Definition (HD) video codecs. It is the world’s first fully-programmable video coding solution for Full HD (1080p).
  
  
• Menta unveils the second generation of its embedded-FPGA (eFPGA) IP (Monday Nov. 12, 2007)
  The Menta’s eFPGA IP is a customizable domain-specific programmable core made with dedicated Look-Up-Tables (LUT), and according to the targeted applications, some additional hard macro blocks (multiplier, memory…) can be plugged inside the core to increase speed, reduce power and area.
  
  
• Microtronix Announces Video LVDS SerDes IP Core for HDTV Applications (Wednesday Nov. 07, 2007)
  Microtronix® today announced the launch of the Video LVDS SerDes Transmitter / Receiver IP Core targeted at the burgeoning high resolution 1080p 100/120 LCD panel display systems.
  
  
• TranSwitch Introduces High-Definition Multimedia Interface IP Cores for Digital Video and Audio Applications (Wednesday Nov. 07, 2007)
  TranSwitch today announced its new HDMI® 1.3 Intellectual Property (IP) cores for high performance digital video and audio applications. The HD-PXL-1.3 transmitter and receiver IP cores will be sampleable in 90 nm CMOS technology.
  
  
• IP Cores, Inc. Ships a Multi-Gigabit Combo AES/XTS, AES/CBC and AES/GCM IP Core for Attached Storage Applications (Wednesday Nov. 07, 2007)
  IP Cores, Inc. today announced shipment of a new silicon IP core supporting the IEEE P1619 storage encryption standard, IEEE 802.1AE MACsec network data encryption standard, and legacy storage AES/CBC encryption. The new GXC3 core enables System on Chip (SoC) vendors to build compact cryptographic processors that support the AES/XTS, AES/GCM, and AES/CBC cryptographic algorithms.
  
  
• Kilopass and Certicom Partner to Deliver Comprehensive Security for High-Bandwidth Digital Content Protection (Tuesday Nov. 06, 2007)
  Certicom KeyInject Integrated into Kilopass XPM Xtend to Protect Against Security Breaches during HDCP Chip Manufacturing Process
  
  
• Mixel Announces Tape-out of the First Complete MIPI D-PHY IP for Mobile Applications (Monday Nov. 05, 2007)
  The MXL-PHY-MIPI includes both the Analog and Digital D-PHY blocks. The IP is designed in Taiwan Semiconductor Manufacturing Company Ltd and Chartered Semiconductor Manufacturing Ltd 0.13um LP digital CMOS process technologies.
  
  
• Aragio Solutions Offers Suite of Programmable GPIO I/O Libraries Supporting 65nm Common Platform Technology Available for Chartered Customers (Monday Nov. 05, 2007)
  ARAGIO announced today the immediate availability of silicon-proven I/O libraries for the 65-nanometer (nm) Common Platform technology process available from Chartered Semiconductor Manufacturing Ltd.
  
  
• Tensilica Unveils Diamond Standard 106Micro Processor; Smallest Licensable 32-bit Core (Monday Nov. 05, 2007)
  The new Diamond Standard 106Micro core takes up only 0.26 mm 2 in a 130-nm G process and only 0.13 mm 2 in a 90-nm G process, which makes it smaller than the ARM7 or Cortex-M3 cores, yet at 1.22 Dhrystone MIPS/MHz, it delivers higher performance than the ARM9E cores.
  
  
• Tensilica Enhances Entire Diamond Standard Processor Core Family, Offers New Features and Memory Power Reductions Up to 30 Percent (Monday Nov. 05, 2007)
  The new second-generation Diamond Standard processors include several new features including additional multiplier and divider functional units, several hardware optimizations that lower memory power by up to 30 percent, and an optional bridge to AXI-based AMBA systems.
  
  
• Noesis Technologies Releases DVB-H Reed Solomon Decoder (Monday Nov. 05, 2007)
  The ntRS-HT and ntRS-CA IP cores are highly parameterizable and can be used in a variety of applications such as IEEE 802.16a, IEEE.802.16e, DVB-S, DVB-H, ITU G.984(GPON), ITU G.975, xDSL, IESS-308, CCSDS e.t.c.
  
  
• Cosmic Circuits announces its WiMO AFE platform for MIMO WiFi and WiMax SoCs (Friday Nov. 02, 2007)
  The AFE platform consists of a dual matched ADC (IQ-ADC), dual matched DAC (IQ-DAC), an auxiliary ADC and DAC for monitoring and control, and a versatile PLL, suitable for portable mobile applications. At low power levels for the receive channel, and with a fast wake-up from standby, it helps extend battery life in portable applications.