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IP / SOC Products News

• Imagination Technologies' Multi-Standard Receiver IP CORE Family Extends Support to 1SEG, 3SEG and Full-SEG ISDB-T (Thursday Nov. 01, 2007)
  The ENSIGMA UCC230 IP core is unique in enabling multiple mobile TV – as well as terrestrial digital and analogue TV and radio – reception standards on a single device whilst delivering exceptionally low power dissipation. It provides the foundation of a highly-integrated mobile TV solution, reducing cost, design risk and time-to-market
  
  
• MoSys Introduces the First in a Family of Gigabit Ethernet Intellectual Property for ICs (Thursday Nov. 01, 2007)
  The MoSys Gigabit PHY IP supports IEEE-defined 10/100/1000 BASE-T Ethernet over Category 5 (CAT 5) twisted pair cables and 10/100 BASE-T Ethernet over CAT 3, 4, and 5 cables. The Gigabit PHY is currently designed in a low power 130nm CMOS and can be readily ported to 65nm and 45nm processes. MoSys offers a multi-port Gigabit PHY with up to 8 integrated ports ready to be integrated with a System-on-Chip (SoC).
  
  
• SD/SDIO/MMC Slave Controller IP Core Enables High Performance SD and MMC Card Design (Thursday Nov. 01, 2007)
  Eureka Technology today announces the immediate availability of SD/SDIO/MMC slave controller core that supports Secure Digital (SD) and Multi-Media Card (MMC). Eureka has provided SD and MMC IP cores to many licensees since 2004. This latest addition of the slave controller completes the product line. A hardware development board for SD/SDIO/MMC development will also be available soon.
  
  
• Imagination Technologies META HTP Multi-Threaded Processor IP Core (Wednesday Oct. 31, 2007)
  Based on META2 architecture the latest generation of Imagination’s highly regarded META™ multi-threaded processor core technology, META HTP extends support for powerful Operating Systems (OS) and applications while providing faster speeds and new architectural enhancements.
  
  
• Evatronix announces NANDFlash-CTRL3 Controller for SoC Designs (Wednesday Oct. 31, 2007)
  NANDFlash-CTRL3 Controller IP provides designers with a fast and efficient arrangement of SLC and MLC Large Block NAND Flash Memory
  
  
• Evatronix unveils an Embedded Internet Subplatform (Monday Oct. 29, 2007)
  Evatronix has announced the immediate availability of its Embedded Internet Subplatform that combines two company IP cores: R8051XC microcontroller and MAC-L Ethernet media access controller with the CMX-MicroNetTM TCP/IP software stack from CMX Systems, Inc.
  
  
• Evatronix adds an ATAIF Software Driver to its configurable ATAIF Host Controller IP (Wednesday Oct. 24, 2007)
  ATAIF driver is a complete software package designed to provide the user with a full access to the functionality provided by Evatronix ATAIF host controller. It allows for an easy access to Mass Storage Devices through ATA/ATAPI 6 protocol.
  
  
• TTP Controller IP in Altera's Low-Cost Cyclone FPGA Families for Aerospace Applications (Tuesday Oct. 23, 2007)
  TTP controller IP implemented with Cyclone II and Cyclone III devices enable seamless subsystem integration for complex safety-critical aircraft networks and systems. The TTP IP has been designed to meet aerospace requirements in compliance with DO-254/DO-178B Level A
  
  
• Mentor Graphics Releases Serial ATA PHY Intellectual Property for SMIC 130 Nanometer Generic Process (Tuesday Oct. 23, 2007)
  The Mentor MSATA PHY S130A IP core comes fully integrated with Mentor’s SATA controllers, targeting both Host and Device applications running at either 1.5Gbps or 3.0Gbps speeds.
  
  
• Chipidea and PLM Unveil New Chip Design Allowing Billions of People to Enjoy HD Content on CRT TVs (Tuesday Oct. 23, 2007)
  The chip’s completion is the result of Chipidea’s analog IP design expertise and years of application-specific experience in video analog front-end (AFE) technology, in combination with PLM’s extensive system-level experience in the research, design, development and manufacturing of video and audio processing chips.
  
  
• Virage Logic Expands Silicon Aware Intellectual Property (IP) Offering with New 65-Nanometer Memory and Logic Products (Monday Oct. 22, 2007)
  This new offering, based on more than two years of early 65nm silicon successes, broadens the company's Silicon Aware IP portfolio and enables semiconductor companies to design faster, lower power and more area efficient System-on-Chips (SoCs) while achieving higher yields.
  
  
• Virage Logic Broadens Its Silicon Aware Intellectual Property (IP) Offering with New Release of the STAR(TM) Memory System (Monday Oct. 22, 2007)
  Introduced in 2001 and successfully used by over 100 companies, this new release adds capabilities to address the challenges of advanced design and process technologies. A dashboard of user-selectable options enables tradeoffs between test time, area, and state-of-the-art diagnostics for optimal design complexity management.
  
  
• Octasic Announces High Performance Asynchronous DSP Core (Thursday Oct. 18, 2007)
  The Opus architecture solves the most pressing issue of the DSP industry, power consumption. DSP manufacturers continue to pack more and more processing capacity into DSPs to meet this challenge but the power consumed by traditional designs is rising faster than the gains in capacity. With Opus, Octasic breaks this barrier by delivering unprecedented power to performance ratios.
  
  
• Think Silicon introduces IPGenius: The first on-line parametrizable IP generation platform (Thursday Oct. 18, 2007)
  IPGenius allows the generation of custom-made IP modules from a selection of modules that can be customised according to users' requirements, packaged and delivered to the end-user via the internet. The tool will host a rapidly expanding portfolio of proprietary, partner and verified commercially friendly opensource Semiconductor IP (SIP) modules, that can be parametrised to user requirements from an easy to use web interface.
  
  
• Rambus Introduces Memory Controller Interface Solution for Industry-standard DDR3 DRAM (Wednesday Oct. 17, 2007)
  The fully integrated hard macro cell provides the physical layer (PHY) interface between the controller logic and DDR3 or DDR2 DRAM devices for data rates of up to 1600 MHz.
  
  
• LogicVision Announces Industry's Most Comprehensive On-Chip eDRAM Test and Repair Solution (Tuesday Oct. 16, 2007)
  LogicVision today announced that its ETMemory(TM) product line now fully supports built-in-self-test and built-in self-repair of embedded DRAMs (eDRAMs).
  
  
• 3Plus1 Technology Announces Availability of CoolEngine Multicore IP Family for Mobile SoC Products (Monday Oct. 15, 2007)
  The first instances of the CoolEngine family comprise two members that take advantage of the intrinsic scaling of the 3Plus1 multiprocessor approach for implementation of JPEG, MPEG, H.263, and H.264 encode and decode operations as well as standard audio applications along with GPS and Bluetooth.
  
  
• Dolphin Integration announces the expansion of its offering in power management (Monday Oct. 15, 2007)
  The Enabler of Mixed-Signal System-on-Chip will launch in the coming weeks a complete line of Virtual Components including high efficiency Direct Current converters, as well as highly integrated battery management and voltage monitoring functions.
  
  
• Dolphin Integration announces its ultra low power, low leakage and High density 65 nm ROMs and RAMs (Thursday Oct. 11, 2007)
  DOLPHIN Integration marks their presence at 65 nm, with the patented tROMet Phoenix, optimized for ultra high density and very low leakage, as well as the spRAM Uranus optimized for Low power and Low leakage.
  
  
• ARM SecurCore Foundry Program Provides Access To 32-bit Smart Card IP (Wednesday Oct. 10, 2007)
  ARM today announced the launch of the new ARM® SecurCore™ Foundry Program, with fabless design houses TMC and HED, and pure-play foundry HHNEC, as the first Partners to enlist in the Program.
  
  
• ARM Unveils Cortex-A9 Processors For Scalable Performance and Low-Power Designs (Wednesday Oct. 03, 2007)
  The ARM Cortex-A9 MPCore™ multicore processor and ARM Cortex-A9 single core processor deliver unprecedented performance within tight power constraints for innovative devices that deliver superior overall functionality, such as smartphones, connected mobile computers, consumer electronics, automotive infotainment, networking and other embedded and enterprise devices.
  
  
• Imagination Technologies Launches Multi-Standard Mobile TV Receiver Core with 1seg ISDB-T Support (Monday Oct. 01, 2007)
  The ENSIGMA UCC224 multi-standard mobile TV IP core enables devices to provide multiple-standard support in the same country and roam between countries with different standards. By supporting multiple standards on the same IP core Imagination’s licensing partners are significantly reducing the total cost of ownership for global mobile TV technology.
  
  
• Impinj Delivers Reprogrammable Nonvolatile Memory IP Breakthrough - AEON/MTP World's First 2.5V Floating-Gate NVM in TSMC's 65 Nanometer Process (Wednesday Sep. 26, 2007)
  AEON/MTP is the first available NVM IP based on floating gate technology with 2.5V transistors. Impinj is also developing AEON/MTP NVM cores in TSMC’s 45 nm processes to address escalating demand from leading-edge system-on-chip (SoC) designers for logic NVM in industry-leading process geometries.
  
  
• GDA Technologies Announces Availability of HiGig IP (Wednesday Sep. 26, 2007)
  GDA Technologies’ offering of the HiGig core is an enhanced version of the current 10G Ethernet MAC core, adding a robust HiGig protocol feature. The basic transmission method utilizes the Preamble field of an Ethernet packet with four bytes of interpacket gap to allow HiGig ports to connect to other HiGig ports. GDA has already successfully implemented the system on Xilinx’s Virtex-5 FPGAs.
  
  
• Synopsys DesignWare USB 2.0 NanoPHY and PCI Express PHY IP Achieve Compliance in SMIC's 130-NM Process Technology (Thursday Sep. 20, 2007)
  Synopsys today announced that its DesignWare® USB 2.0 nanoPHY IP achieved USB logo certification and its PCI Express (PCIe) PHY IP passed compliance testing when implemented in SMIC's popular 130-nm G process technology.
  
  
• Denali Software and Tokyo Electron Device Unveil New DFI Compatible DDR2 SDRAM PHY for Xilinx FPGA (Thursday Sep. 20, 2007)
  Tokyo Electron Device, Ltd. (TED) ASIC customers now have access to DDR PHY designs, in 90-nm process technologies and below, that integrate seamlessly with other DFI compatible designs, including Denali's Databahn(TM) DDR memory controller products.
  
  
• Fujitsu and Denali Software Collaborate to Develop DFI Compatible DDR PHY Macro (Wednesday Sep. 19, 2007)
  The DDR PHY utilizes the DFI specification which defines a common interface between the conventional proprietary memory controller logic and DDR PHY designs, which reduces design and integration costs for developing DDR DRAM memory systems, and reduces overall time-to-market.
  
  
• IMEC Sets New Record for 9bit, 50MSamples/s SAR ADC with a Figure of Merit of 65fJ (Wednesday Sep. 19, 2007)
  The novel IMEC SAR ADC design is especially suited for nomadic applications in the IT realm. It is implemented in pure digital CMOS technology, making it very well suited for scaling to the 45nm CMOS node and below. The design is available as 'white box IP' for transfer to the industry.
  
  
• Chipidea Delivers First TSMC Qualified USB High-Speed PHY IP on 65nm GP Process Technology (Tuesday Sep. 18, 2007)
  The certified High-Speed USB PHY core runs at 2.5 volts and is compliant with the USB 2.0 standard, including 5 volt protection on the D+ D- ports. The unique analog programmability of the IP is a key feature that enables system-on-chip (SoC) designers to fine tune the complete system for optimized performance.
  
  
• Xilinx Enhances Wireless Infrastructure Solutions With New Virtex-5 FPGA IP for CPRI and OBSAI Standards (Monday Sep. 17, 2007)
  Xilinx today announced immediate availability of two high performance wireless connectivity LogiCORE solutions optimized for Xilinx(R) 65nm Virtex(TM)-5 LXT and SXT FPGAs, compliant with CPRI v2.1 and OBSAI RP3 & RP3-01 v4.0 connectivity standards.