High Performance 64-bit RISC-V Multi-Core Application Processor
IP / SOC Products News
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Altera and PLDA Announce Audio Solution for Broadcast Market (Friday Sep. 07, 2007)
Altera and PLDA SAS today announced an expanded collaboration to bring flexible solutions to the professional audio/video broadcast market. The initial result of this collaboration is the introduction of the first of a new line of intellectual property (IP) cores and the audio sample converter (SRC), which is now available free of IP license fees to qualified customers of Altera’s Stratix® and Cyclone® FPGA device families.
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Xilinx and MindWay Announce New Portfolio of Broadcast Modulation Solutions (Friday Sep. 07, 2007)
The new IP cores support DVB-T/H, DVB-C, DVB-S and ATSC 8-VSB transmission standards, enabling design engineers to quickly adopt DVB technology in their design while drastically reducing overall system cost.
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Xilinx and intoPIX Team to Deliver Latest IP Solutions to Broadcast Industry (Friday Sep. 07, 2007)
The intoPIX JPEG2000 encoding algorithm running on a Xilinx Virtex-5 FPGA, allows encoding at up to 120 frames-per-second (fps), over 20 percent faster than previous solutions. This creates the potential to create a multi-stream encoder delivering up to four channels of HD-SDI image management at 30 fps.
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Xilinx Announces High Definition Real-Time MPEG4 AVC/H.264 Encoder Solution (Friday Sep. 07, 2007)
The solution is based on ATEME's high definition H.264 encoding platform, ideal for markets such as IPTV and satellite broadcast which require the best video quality at the lowest possible bit rates. The Virtex-5 FPGA based solution delivers the programmability and computing power required to deliver high definition video quality.
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Xilinx and Barco Announce Single-Chip JPEG2000 Implementation (Friday Sep. 07, 2007)
Based on successful implementation of Barco Silex JPEG2000 cores on Xilinx® Virtex(TM)-5 FPGAs, the solutions significantly reduce the cost of broadcast and digital cinema initiative (DCI) archiving, post-production, distribution, and server systems.
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Mentor Graphics Offers PCI Express Controller and AMBA Bridge Intellectual Property Solutions (Wednesday Sep. 05, 2007)
Mentor Graphics Corporation today announced availability of PCI Express® (PCIe®) Controller and AMBA® Bridge intellectual property (IP) solutions for the rapid and cost-effective integration into ASIC and System-On-Chip (SoC) platforms.
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Tensilica and Tallika Announce Secure SOC FPGA Platform (Wednesday Sep. 05, 2007)
This fully verified and silicon proven hardware/software platform is ideal for any design team that needs a full implementation of RSA( including encryption, decryption, and key-pair generation acceleration) and/or an SOC with integrated hardware security functions.
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Faraday Implements 640 MHz ARM926EJ-S Hard Core Using UMC 90 nm Process Technology (Wednesday Sep. 05, 2007)
Faraday's ARM926EJ-S™ hard core runs at 400 MHz under the worst case condition and could reach ultra high clock speed up to 640 MHz in a typical case with relatively low power consumption and small area. Currently the 90 nm hard core is ready, and its test chips will be available in October, 2007.
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Rambus and Cadence Collaborate and Deliver Fully Integrated and Independently Verified PCI Express Solutions (Tuesday Sep. 04, 2007)
The two companies have collaborated and now offer highly adaptable PCI Express digital cores and PHY IP from Rambus, tightly integrated and verified with Cadence verification IP.
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Digital Blocks Extends the DB9000 TFT LCD Controller IP Core Family with the availability of the DB9000OCP for the Open Core Protocol 2.2 Interconnect (Monday Sep. 03, 2007)
Specifically targeted for TFT LCD panels and the Open Core Protocol 2.2 On-Chip Interconnect, the DB9000OCP is an out-of-the-box synthesizable soft IP Core for ASIC and ASSP design teams with display system requirements.
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ASIC Architect Announces the Availability of AMBA 2 AHB to PCI Express Bridge (Wednesday Aug. 29, 2007)
The solution product has passed PCI Express Compliance and Interoperability testing in PCI-SIG compliance workshop. This solution enables SoC designers to plug-in PCI Express Controller Core into AMBA 2 AHB system bus. This directly leads to low design implementation risk.
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Acacia Semiconductor Announces a New Family of Best-in-Class High-Speed 10-bit ADC IPs Silicon Proven in a 130nm Process (Tuesday Aug. 28, 2007)
The new product family consists of six different ADC IPs that feature 10-bit resolution, single and dual channel solutions, sampling rates from 20MS/s up to 160MS/s and 300MHz sample-and-hold circuits.
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Kilopass Announces Embedded Non-Volatile Memory for 65 nm Low Power and 65 nm General Purpose Processes (Thursday Aug. 23, 2007)
Kilopass XPM technology is the world’s first high-density embedded NVM technology verified in silicon and available for design in 65 nm standard logic CMOS processes. Kilopass is also making XPM-65LP and XPM-65G+ evaluation kits available to its customers.
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Salamander Error Correction announces 1 Gbps Viterbi decoder (Wednesday Aug. 22, 2007)
Salamander Error Correction announced today the availability of the SALxx304d, a very high speed (1 Gbps) Viterbi decoder for telecommunications and high speed wireless networking applications.
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SNOWBUSH microelectronics Announces Silicon Verified 6-Bit, 2.5 GSPS, ADC IP Core in 90nm CMOS Process (Tuesday Aug. 21, 2007)
SNOWBUSH's 6-bit ADC is compact, low-power, and by utilizing its high bandwidth sample-and-hold front-end, it maintains excellent dynamic performance throughout the full range of input frequencies. The ADC features INL of 0.59 LSB, DNL of 0.51 LSB, and ENOB of 5.2 or greater for sampling clock frequencies up to 2.5 GHz. The ADC occupies a silicon area of 0.43 square millimeters.
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Elliptic and Impinj Collaboration Bolsters System-On-Chip Digital Content Protection (Monday Aug. 20, 2007)
Elliptic Semiconductor, Inc., and Impinj, Inc., today announced an agreement to collaboratively develop a secure, standards-based system-on-chip (SoC) reference architecture for content protection applications such as digital rights management (DRM) and conditional access. The reference architecture integrates Elliptic’s embedded security module (ESM) and Impinj’s AEON® multi-time programmable nonvolatile memory (NVM) core to counteract embedded system threats such as reverse chip engineering and cryptographic algorithm security breaches.
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Faraday Introduces Next Generation ARM v5 Compliant Ultra High Performance Processor - FA626TE (Tuesday Aug. 14, 2007)
The first hard core which reaches the worst case clock speed at 533MHz is available in UMC 0.13um process. Faraday expects its next versions for 90nm in UMC, running 667MHz and 800MHz in worst case, to be available in initial Q4 and the end of 2007 respectively.
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Tallika Announces Asymmetric Public-Key Cryptography Acceleration Solution (Monday Aug. 13, 2007)
Tallika’s solution includes Verilog RTL/Testbench for user configurable 4096/2048/1536/1024/512 bit native Exponentiation engine for accelerating large number mathematical operations. The solution is available on the Company’s Xilinx LX160 Virtex 4 based Secure SOC FPGA Platform for evaluation and product development purposes. The company also disclosed that its solution is already in silicon in 0.13u TSMC process.
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New VRaptor-Based ARC Video Subsystems Set the Standard for High Quality Video Encode in Consumer Devices (Monday Aug. 13, 2007)
ARC International today set a new standard for high-quality video encoding with the introduction of five new members of the ARC® Video Subsystem family: AV 417V, AV 407V, AV406V, AV 404V, and AV 402V. All include ARC's new patent-pending technology "dynamic adaptive encoding" that enables encoding of video streams at the lowest power.
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AKA's MIL-STD 1553 RT core validated by leading independent test house (Friday Aug. 10, 2007)
Advanced Knowledge Associates today announced that it has achieved certification for its MIL-STD-1553B remote terminal (RT) core. First published as an Air Force standard in 1973 to define certain data bus requirements for information transfer, MIL-STD-1553 continues to be used heavily today in mission-critical systems, such as in avionics, space and defense.
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Altera Delivers PCI-SIG Compliant x1 and x4 PCI Express Solution Supporting Arria GX FPGAs (Tuesday Aug. 07, 2007)
Altera® Arria GX FPGAs, combined with Altera’s PCI Express x4 MegaCore® intellectual property (IP) function, are an integral part of the lowest-cost, PCI-SIG-compliant development kit in the industry.
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Silicon Interfaces ships the new SI16FWA20 Link Layer Controller Fire Wire IP (Thursday Aug. 02, 2007)
Silicon Interfaces Link Layer Controller core is a functional block available for insertion into an ASIC design, which supports the IEEE 1394a-2000 Draft specifications for a high-speed serial bus. The SI16FWA20 Link core is implemented using VHDL synthesizable code to provide portability across Silicon Interfaces Gate Array and Cell-Based ASIC technologies.
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Altera Offers Complete USB 2.0 Device Controller Solution (Wednesday Aug. 01, 2007)
Altera today expanded its intellectual property (IP) portfolio with the introduction of a complete USB 2.0 Hi-/Full-Speed Device Controller solution from System Level Solutions (SLS). This new solution is comprised of a soft IP core, software and class drivers, and SLS’s Snap-On PHY daughtercards. The daughtercards are designed for use exclusively with Altera® development kits.
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Chipidea Step-Down DC-DC Converter Core Supports 4.2V External Supply Voltage in Generic CMOS Process Using 3.3V Devices (Tuesday Jul. 31, 2007)
The CI2512tl Step-Down DC-DC Converter IP core is the latest offering from the company with the most comprehensive catalog of general purpose, programmable power management IP cores. This IP core allows SoC designers to integrate DC-DC converter functionality into their designs and avoid the additional expense of higher voltage process options.
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Silicon Interfaces announces the release of its new SI85SCC30-A Serial Communication Controller IP (Friday Jul. 27, 2007)
Silicon Interfaces SI85SCC30-A Serial Communication Controller (SCC) is a versatile full-duplex, dual-channel multi-protocol data communication peripheral, with triple-buffered Receiver and double buffered Transmitter. SI85SCC30-A is a refined and upgraded version of its predecessor, SI85SCC30. This SCC is a VHDL-based soft IP, which can be targeted to either Gate Arrays or Cell-based ASICs.
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Arasan Chip Systems Releases SLIMbus IP Compliant with the MIPI Version 1.0 Specification (Thursday Jul. 26, 2007)
The new SLIMbus IP is optimized for customer applications providing a number of hardware/software partitioning choices depending on the SLIMbus operation needed. Arasan offers a complete SLIMbus Software Stack for supporting the SLIMbus protocol and software customization services to support legacy buses like I2C, I2S, SPI and UARTs.
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Faraday Announces UWB MAC Solution for Wireless Applications that Require High-Throughput (Wednesday Jul. 25, 2007)
Faraday Technology Corporation, a leading ASIC and silicon IP provider, today announced the availability of the Ultra-Wideband (UWB) Medium Access Controller (MAC) solution. By integrating UWB MAC into the SoC designs, designers can easily achieve 200Mbps+ throughput and significantly reduce the chip's pin counts.
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Global Unichip Presents the ARM926 Solution Achieving a 400MHz Performance (Wednesday Jul. 25, 2007)
Global Unichip today announced the success of delivering the ARM926 solution with a 400MHz performance on TSMC 0.13G process to a leading developer of navigation processor solutions for mobile navigation devices. Same effort has achieved a 650MHz performance on the ARM1136 solution with TSMC 0.13LV process.
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Kilopass Announces 90nm On-Chip Embedded Non-Volatile Memory IP for SoC Designs Using General Purpose and Low Power Standard Logic CMOS (Tuesday Jul. 24, 2007)
Kilopass' silicon-proven, low cost and highly secure XPM(TM) memory technology offers the benefits of field programmability of NVM implemented in standard-logic CMOS processes, including 180 nm, 130 nm and 90 nm. Targeted SOC applications include: Digital Rights Management (DRM), High-bandwidth Digital Content Protection (DHCP), encryption keys, electronic security, mixed-signal trim and calibration, memory and pixel repair, encryption keys, firmware parameters, hardware configuration and (secure) boot code storage.
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Altera Delivers First FPGA-Based IP Support for Key Industrial Ethernet Protocols (Tuesday Jul. 24, 2007)
Altera today announced FPGA-based support for Ethernet communications protocols used in industrial automation applications, including ProfiNet, Ethernet/IP, Modbus-IDA, EtherCAT, SERCOS III Interface, and Ethernet Powerlink. Intellectual property (IP) cores for these key communications protocols can now be implemented on Altera’s low-cost Cyclone® series FPGAs.