IP / SOC Products News
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Athena Announces the First Public Key Microprocessor (Tuesday Jul. 24, 2007)
The Athena Group today announced the introduction of its T5200 TeraFire® security accelerator, the first programmable public key microprocessor. Coupling Athena's ultra-efficient arithmetic technology and a comprehensive instruction set, the T5200 delivers both performance and flexibility for applications ranging from low speed data terminals to high performance network security appliances.
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Ridgetop Group Announces Availability of a Sensor for Real-Time Detection of Solder-Joint Faults in Programmed, Operational FPGAs (Monday Jul. 23, 2007)
The SJ-BIST product consists of a Verilog softcore that is synthesizable into a customer’s FPGA, along with full documentation and application assistance. The product is a new addition to Ridgetop’s InstaBIST™ family of built-in self test IP solutions. IP Licenses are available.
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Pentek Adds DDC and Interpolation Filter IP Cores to its Dual Digital Transceiver Module, Greatly Boosting Bandwidth Range (Monday Jul. 23, 2007)
Pentek today released its Model 7140-420 Dual Digital Transceiver with Wideband Digital Downconverter (DDC) Core and Interpolation Filter. This is a complete software radio system in a PMC/XMC module.
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ARM And Intrinsity Boost Performance Of CORTEX-R4 Processor (Monday Jul. 23, 2007)
ARM and Intrinsity, Inc., today announced their agreement to produce high-performance implementations of the ARM® Cortex™ family of processors. The first of these will be implementations of the Cortex-R4 processor operating at around twice the frequency achievable using standard synthesis techniques on the same silicon process. The Cortex-R4X processor implementations are available for licensing from ARM immediately.
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GDA announces the availability of PCI Express Gen 2 Controller (GPEX-2) IP (Friday Jul. 20, 2007)
GPEX-2 IP is a flexible and configurable design targeted for end-point, root complex, switch and bridge implementation. The controller’s architecture is carefully crafted for optimal link utilization, latency, reliability, power consumption, and foot print.
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Anagram Releases Digital PureLogic IP Core (Thursday Jul. 19, 2007)
The ANAGRAM Digtial PureLogic family of products is based on patented digital filtering and delta-sigma technology and is ideal for applications requiring low power, high levels of integration and precise reconstruction of analog signals. The target technologies include TSMC 0.13um process and below; however all IP blocks are fully digital and therefore are easily portable to other processes.
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Lightspeed Logic announces Manufacturability-Optimized Reconfigurable Logic IP for 65nm and 45nm (Wednesday Jul. 18, 2007)
Lightspeed Logic today announced a new generation of Lightspeed Logic’s Reconfigurable Logic IP for the 65nm and 45nm process nodes. In addition to providing increased flexibility in chip architecture, significant reduction in design cost and rapid time-to-market, the new Manufacturability-Optimized Reconfigurable Logic brings significant benefits to customers designing in advanced geometries.
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EtherCAT Real-Time Protocol IP Support Now Available on Altera's Low-Cost Cyclone III FPGAs (Wednesday Jul. 18, 2007)
Giving industrial equipment designers greater flexibility in implementing real-time Ethernet communications, Altera Corporation today announced intellectual property (IP) support for the EtherCAT protocol from the EtherCAT Technology Group. Previously qualified on Cyclone® II devices, the IP now targets Altera’s new low-cost, low-power Cyclone III FPGAs.
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Dolphin Integration releases a High-resolution, low-noise ADC for sensor applications (Wednesday Jul. 18, 2007)
Dolphin integration announces the availability of their new high-resolution measurement ADC, to be embedded into SoCs for low frequency Sensor applications and Mems. SensADC-16.02 covers optimally the needs of measurement applications with stringent requirements in terms of noise management: blood pressure sensors or weight scales for medical markets, as well as all kind of high-resolution wireless sensors.
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Chipidea Flexible Mixed-Signal IP Platform Architecture Provides Unprecedented Analog Integration (Wednesday Jul. 18, 2007)
Chipidea today announced the industry’s first Flexible Mixed-Signal IP Platform Architecture™ (FLEMIA), a highly innovative approach to integrating multiple blocks of analog functionality into a single chip to streamline electronic system design. Leveraging Chipidea’s extensive, silicon-proven portfolio of analog IP, the FLEMIA platform offers an unprecedented level of analog circuit integration and configurability for electronic communication and consumer applications.
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Denali Announces World's Fastest ECC Solution for NAND Flash Systems (Tuesday Jul. 17, 2007)
Denali Software today announced that Beceem Communications has incorporated its Databahn™ DDR memory controller into the first commercially available terminal chipset for the latest Mobile WiMAX standard.
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Kilopass Announces Collaboration with TSMC in Embedded Non-volatile Memory Technology and Qualification of 0.13-micron Process Technology (Monday Jul. 09, 2007)
Kilopass Technology today announced that it is collaborating with TSMC in developing Kilopass XPM NVM one-time programmable (OTP) IP, and it has successfully qualified its XPM on TSMCs 0.13-micron CMOS logic process technology. Kilopass XPM passed TSMCs rigorous quality standard set that includes over 1000 hours of high-temperature operating life tests.
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Wipro-NewLogic releases next generation Bluetooth IP (Wednesday Jul. 04, 2007)
Wipro-NewLogic's Bluetooth 2.0 + EDR IP is upgradeable by software to next generation Bluetooth 2.1 + EDR and will enable a new range of applications such as high definition audio streaming and transfer of large files. It will significantly increase battery life for applications such as Bluetooth headsets
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Synopsys Teams With UMC to Port Mixed-Signal Connectivity IP to 90- and 65-Nanometer Process Technologies (Thursday Jun. 28, 2007)
Synopsys today announced that it has teamed with UMC to port the Synopsys DesignWare USB 2.0, PCI Express, SATA and XAUI PHY semiconductor intellectual property (IP) to UMC's 90-nanometer (nm) and 65-nm technologies
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PLDA Breakthrough Demonstration of PCIe Gen 2 in Working Silicon Achieves Industry's Highest Throughput (Wednesday Jun. 27, 2007)
During the demo, the PCIe link was established at 5 GHz and some of the industry’s best known companies were able to see measured simultaneous throughput of 350 MB/s (write to the server memory) and 380 MB/s (read to server memory)
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Faraday Launches Silicon-Proven DDR2 Memory Physical Interface IP (Tuesday Jun. 26, 2007)
Faraday's DDR2 PHY IP, a reliable, cost-effective, and easy-to-integrate memory interface solution, enables semiconductor companies, in a timely manner, to make high performance DDR2 memory interface System-on-Chips (SoCs) for their consumer, automotive, industrial and medical applications
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Lattice and PLD Applications Announce Partnership For PCI Express Connectivity Solutions (Monday Jun. 25, 2007)
PLDA Delivers PCI XpressLite Core for LatticeECP2M FPGAs; Partnership Focused on Expansion of Connectivity Solutions for Lattice Devices
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Xilinx Announces Scalable LogiCORE FlexRay controller IP (Tuesday Jun. 19, 2007)
Xilinx announced today immediate availability of the industry's first single-channel LogiCORE(TM) FlexRay(TM) controller IP, optimized for the Xilinx(R) Automotive (XA) Spartan(TM)-3 generation devices.
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IP Cores, Inc. Announces three low-latency Fast Fourier Transform IP cores for SoC applications in the OFDM-based communications (WiMAX, MBOA, IEEE 802.11) and GPS fields (Tuesday Jun. 19, 2007)
FFT64 core and two versions of FFT1024 are very compact and provide parameterized bit width with throughput of 1 sample per clock
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Jetstream Algorithms become NIST Certified and are now FIPS 140-2 Ready (Thursday Jun. 14, 2007)
Jetstream Media Technologies announced today that the algorithms of its security IP cores have successfully passed the Cryptographic Algorithm Validation Program (CAVP), a strict governmental testing program for the validation of semiconductor algorithms
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IP Cores, Inc. Delivers a 10 Gbps AES-GCM FPGA Implementation (Tuesday Jun. 12, 2007)
IP Cores, Inc. announces an FPGA implementation of the AES Galois/Counter Mode (GCM) supporting the IEEE 802.1ae standard with real-life throughput exceeding 10 Gbps for all Ethernet frame sizes.
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Sidense Qualifies 1T-Fuse(TM) in UMC's 130nm Process (Monday Jun. 11, 2007)
By qualifying the NVM IP, a valuable memory addition to the foundry's IP Alliance Program, UMC's customers now have access to a low-cost, highly secure embedded NVM for applications such as electrical fuse replacement, flash and mask-programmable ROM replacement, code storage, RFID, unique ID, encryption, key storage, HDMI, and digital rights management (DRM).
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Alma Technologies launches its new generation JPEG 2000 Encoder Core (Monday Jun. 11, 2007)
Built on already-proven code, the new generation of the JPEG2k-E Encoder Core is a major advance that improves processing and makes it significantly easier to integrate JPEG 2000 in ASIC or FPGA-based systems.
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Digital Blocks Extends the DB9000 TFT LCD Controller IP Core Family with the availability of the DB9000AHB for the AMBA 2.0 Interconnect (Tuesday Jun. 05, 2007)
The DB9000AHB IP Core targets systems-on-chip (SoC) ASSP, ASIC, and FPGA designs containing ARM embedded processors and the AMBA 2.0 AHB on-chip bus, as well as other processors that support the AHB bus, and system requirements for a TFT LCD panel
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CAST JPEG 2000 Encoder Core now Faster and More Capable (Monday Jun. 04, 2007)
Second-generation core nearly doubles throughput speed and now integrates Tier-1 and Tier-2 functions to handle the biggest HDTV images without an external processor
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Lightspeed Logic collaborates with Cadence to deliver Reconfigurable Logic Reference Flow (Friday Jun. 01, 2007)
Lightspeed Logic today announced immediate availability of the 65-nanometer Common Power Format (CPF)-enabled reference flow for Lightspeed Logic’s Reconfigurable Logic IP. This reference flow enables SOC designers to accelerate time-to-market for low-power designs using Lightspeed Logic’s Reconfigurable Logic IP.
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Chipidea's New USB PHY Architecture for 1.8V Devices Offers Industry's Lowest Power Consumption for SoC Designers (Friday Jun. 01, 2007)
Chipidea, the world's leading provider of analog/mixed-signal subsystems and intellectual property (IP), today introduced a new generation USB physical layer architecture using 1.8V IO devices that offers the industry's lowest power consumption for System-on-Chip (SoC) designs in the 65nm and 45nm advanced technology nodes.
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CEVA Announces Next Generation CEVA-TeakLite-III DSP Architecture Featuring Native 32-Bit Processing (Thursday May. 31, 2007)
Targeting next-generation Hi-Fi audio applications, the CEVA-TeakLite-III inherently supports 32-bit data processing functions with multiple precision points and offers an enlarged 64-bit data memory bandwidth. A FFT accelerator further boosts audio performance and reduces power consumption. For example, a 7.1 channel Dolby Digital Plus decoder would consume only 15% of the core's available MHz at a 90nm process, compared to 47% for its predecessor, the CEVA-TeakLite.
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Synopsys Announces the Industry's First Comprehensive SATA AHCI IP Solution (Wednesday May. 30, 2007)
The DesignWare SATA AHCI core is compliant with the SATA 2.6 specification and AHCI 1.1 specification, and includes an ARM AMBA 2-compliant subsystem interface. The DesignWare SATA AHCI core has been verified against the industry-standard AHCI software drivers provided as part of the Linux® and Windows Vista™ operating systems.
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Denali Announces Databahn DDR3 Memory Controller IP Product (Tuesday May. 29, 2007)
Denali's Databahn memory controller IP enables optimal performance for a wide range of DDR3 memory system applications including video and media processing, signal and network processing, and various consumer product applications.