D&R Headline News | Most Popular | SoC News Alerts | |

IP / SOC Products News

• Altera Offers Complete USB 2.0 Device Controller Solution (Wednesday Aug. 01, 2007)
  Altera today expanded its intellectual property (IP) portfolio with the introduction of a complete USB 2.0 Hi-/Full-Speed Device Controller solution from System Level Solutions (SLS). This new solution is comprised of a soft IP core, software and class drivers, and SLS’s Snap-On PHY daughtercards. The daughtercards are designed for use exclusively with Altera® development kits.
  
  
• Chipidea Step-Down DC-DC Converter Core Supports 4.2V External Supply Voltage in Generic CMOS Process Using 3.3V Devices (Tuesday Jul. 31, 2007)
  The CI2512tl Step-Down DC-DC Converter IP core is the latest offering from the company with the most comprehensive catalog of general purpose, programmable power management IP cores. This IP core allows SoC designers to integrate DC-DC converter functionality into their designs and avoid the additional expense of higher voltage process options.
  
  
• Silicon Interfaces announces the release of its new SI85SCC30-A Serial Communication Controller IP (Friday Jul. 27, 2007)
  Silicon Interfaces SI85SCC30-A Serial Communication Controller (SCC) is a versatile full-duplex, dual-channel multi-protocol data communication peripheral, with triple-buffered Receiver and double buffered Transmitter. SI85SCC30-A is a refined and upgraded version of its predecessor, SI85SCC30. This SCC is a VHDL-based soft IP, which can be targeted to either Gate Arrays or Cell-based ASICs.
  
  
• Arasan Chip Systems Releases SLIMbus IP Compliant with the MIPI Version 1.0 Specification (Thursday Jul. 26, 2007)
  The new SLIMbus IP is optimized for customer applications providing a number of hardware/software partitioning choices depending on the SLIMbus operation needed. Arasan offers a complete SLIMbus Software Stack for supporting the SLIMbus protocol and software customization services to support legacy buses like I2C, I2S, SPI and UARTs.
  
  
• Faraday Announces UWB MAC Solution for Wireless Applications that Require High-Throughput (Wednesday Jul. 25, 2007)
  Faraday Technology Corporation, a leading ASIC and silicon IP provider, today announced the availability of the Ultra-Wideband (UWB) Medium Access Controller (MAC) solution. By integrating UWB MAC into the SoC designs, designers can easily achieve 200Mbps+ throughput and significantly reduce the chip's pin counts.
  
  
• Global Unichip Presents the ARM926 Solution Achieving a 400MHz Performance (Wednesday Jul. 25, 2007)
  Global Unichip today announced the success of delivering the ARM926 solution with a 400MHz performance on TSMC 0.13G process to a leading developer of navigation processor solutions for mobile navigation devices. Same effort has achieved a 650MHz performance on the ARM1136 solution with TSMC 0.13LV process.
  
  
• Kilopass Announces 90nm On-Chip Embedded Non-Volatile Memory IP for SoC Designs Using General Purpose and Low Power Standard Logic CMOS (Tuesday Jul. 24, 2007)
  Kilopass' silicon-proven, low cost and highly secure XPM(TM) memory technology offers the benefits of field programmability of NVM implemented in standard-logic CMOS processes, including 180 nm, 130 nm and 90 nm. Targeted SOC applications include: Digital Rights Management (DRM), High-bandwidth Digital Content Protection (DHCP), encryption keys, electronic security, mixed-signal trim and calibration, memory and pixel repair, encryption keys, firmware parameters, hardware configuration and (secure) boot code storage.
  
  
• Altera Delivers First FPGA-Based IP Support for Key Industrial Ethernet Protocols (Tuesday Jul. 24, 2007)
  Altera today announced FPGA-based support for Ethernet communications protocols used in industrial automation applications, including ProfiNet, Ethernet/IP, Modbus-IDA, EtherCAT, SERCOS III Interface, and Ethernet Powerlink. Intellectual property (IP) cores for these key communications protocols can now be implemented on Altera’s low-cost Cyclone® series FPGAs.
  
  
• Athena Announces the First Public Key Microprocessor (Tuesday Jul. 24, 2007)
  The Athena Group today announced the introduction of its T5200 TeraFire® security accelerator, the first programmable public key microprocessor. Coupling Athena's ultra-efficient arithmetic technology and a comprehensive instruction set, the T5200 delivers both performance and flexibility for applications ranging from low speed data terminals to high performance network security appliances.
  
  
• Ridgetop Group Announces Availability of a Sensor for Real-Time Detection of Solder-Joint Faults in Programmed, Operational FPGAs (Monday Jul. 23, 2007)
  The SJ-BIST product consists of a Verilog softcore that is synthesizable into a customer’s FPGA, along with full documentation and application assistance. The product is a new addition to Ridgetop’s InstaBIST™ family of built-in self test IP solutions. IP Licenses are available.
  
  
• Pentek Adds DDC and Interpolation Filter IP Cores to its Dual Digital Transceiver Module, Greatly Boosting Bandwidth Range (Monday Jul. 23, 2007)
  Pentek today released its Model 7140-420 Dual Digital Transceiver with Wideband Digital Downconverter (DDC) Core and Interpolation Filter. This is a complete software radio system in a PMC/XMC module.
  
  
• ARM And Intrinsity Boost Performance Of CORTEX-R4 Processor (Monday Jul. 23, 2007)
  ARM and Intrinsity, Inc., today announced their agreement to produce high-performance implementations of the ARM® Cortex™ family of processors. The first of these will be implementations of the Cortex-R4 processor operating at around twice the frequency achievable using standard synthesis techniques on the same silicon process. The Cortex-R4X processor implementations are available for licensing from ARM immediately.
  
  
• GDA announces the availability of PCI Express Gen 2 Controller (GPEX-2) IP (Friday Jul. 20, 2007)
  GPEX-2 IP is a flexible and configurable design targeted for end-point, root complex, switch and bridge implementation. The controller’s architecture is carefully crafted for optimal link utilization, latency, reliability, power consumption, and foot print.
  
  
• Anagram Releases Digital PureLogic IP Core (Thursday Jul. 19, 2007)
  The ANAGRAM Digtial PureLogic family of products is based on patented digital filtering and delta-sigma technology and is ideal for applications requiring low power, high levels of integration and precise reconstruction of analog signals. The target technologies include TSMC 0.13um process and below; however all IP blocks are fully digital and therefore are easily portable to other processes.
  
  
• Lightspeed Logic announces Manufacturability-Optimized Reconfigurable Logic IP for 65nm and 45nm (Wednesday Jul. 18, 2007)
  Lightspeed Logic today announced a new generation of Lightspeed Logic’s Reconfigurable Logic IP for the 65nm and 45nm process nodes. In addition to providing increased flexibility in chip architecture, significant reduction in design cost and rapid time-to-market, the new Manufacturability-Optimized Reconfigurable Logic brings significant benefits to customers designing in advanced geometries.
  
  
• EtherCAT Real-Time Protocol IP Support Now Available on Altera's Low-Cost Cyclone III FPGAs (Wednesday Jul. 18, 2007)
  Giving industrial equipment designers greater flexibility in implementing real-time Ethernet communications, Altera Corporation today announced intellectual property (IP) support for the EtherCAT protocol from the EtherCAT Technology Group. Previously qualified on Cyclone® II devices, the IP now targets Altera’s new low-cost, low-power Cyclone III FPGAs.
  
  
• Dolphin Integration releases a High-resolution, low-noise ADC for sensor applications (Wednesday Jul. 18, 2007)
  Dolphin integration announces the availability of their new high-resolution measurement ADC, to be embedded into SoCs for low frequency Sensor applications and Mems. SensADC-16.02 covers optimally the needs of measurement applications with stringent requirements in terms of noise management: blood pressure sensors or weight scales for medical markets, as well as all kind of high-resolution wireless sensors.
  
  
• Chipidea Flexible Mixed-Signal IP Platform Architecture Provides Unprecedented Analog Integration (Wednesday Jul. 18, 2007)
  Chipidea today announced the industry’s first Flexible Mixed-Signal IP Platform Architecture™ (FLEMIA), a highly innovative approach to integrating multiple blocks of analog functionality into a single chip to streamline electronic system design. Leveraging Chipidea’s extensive, silicon-proven portfolio of analog IP, the FLEMIA platform offers an unprecedented level of analog circuit integration and configurability for electronic communication and consumer applications.
  
  
• Denali Announces World's Fastest ECC Solution for NAND Flash Systems (Tuesday Jul. 17, 2007)
  Denali Software today announced that Beceem Communications has incorporated its Databahn™ DDR memory controller into the first commercially available terminal chipset for the latest Mobile WiMAX standard.
  
  
• Kilopass Announces Collaboration with TSMC in Embedded Non-volatile Memory Technology and Qualification of 0.13-micron Process Technology (Monday Jul. 09, 2007)
  Kilopass Technology today announced that it is collaborating with TSMC in developing Kilopass XPM NVM one-time programmable (OTP) IP, and it has successfully qualified its XPM on TSMCs 0.13-micron CMOS logic process technology. Kilopass XPM passed TSMCs rigorous quality standard set that includes over 1000 hours of high-temperature operating life tests.
  
  
• Wipro-NewLogic releases next generation Bluetooth IP (Wednesday Jul. 04, 2007)
  Wipro-NewLogic's Bluetooth 2.0 + EDR IP is upgradeable by software to next generation Bluetooth 2.1 + EDR and will enable a new range of applications such as high definition audio streaming and transfer of large files. It will significantly increase battery life for applications such as Bluetooth headsets
  
  
• Synopsys Teams With UMC to Port Mixed-Signal Connectivity IP to 90- and 65-Nanometer Process Technologies (Thursday Jun. 28, 2007)
  Synopsys today announced that it has teamed with UMC to port the Synopsys DesignWare USB 2.0, PCI Express, SATA and XAUI PHY semiconductor intellectual property (IP) to UMC's 90-nanometer (nm) and 65-nm technologies
  
  
• PLDA Breakthrough Demonstration of PCIe Gen 2 in Working Silicon Achieves Industry's Highest Throughput (Wednesday Jun. 27, 2007)
  During the demo, the PCIe link was established at 5 GHz and some of the industry’s best known companies were able to see measured simultaneous throughput of 350 MB/s (write to the server memory) and 380 MB/s (read to server memory)
  
  
• Faraday Launches Silicon-Proven DDR2 Memory Physical Interface IP (Tuesday Jun. 26, 2007)
  Faraday's DDR2 PHY IP, a reliable, cost-effective, and easy-to-integrate memory interface solution, enables semiconductor companies, in a timely manner, to make high performance DDR2 memory interface System-on-Chips (SoCs) for their consumer, automotive, industrial and medical applications
  
  
• Lattice and PLD Applications Announce Partnership For PCI Express Connectivity Solutions (Monday Jun. 25, 2007)
  PLDA Delivers PCI XpressLite Core for LatticeECP2M FPGAs; Partnership Focused on Expansion of Connectivity Solutions for Lattice Devices
  
  
• Xilinx Announces Scalable LogiCORE FlexRay controller IP (Tuesday Jun. 19, 2007)
  Xilinx announced today immediate availability of the industry's first single-channel LogiCORE(TM) FlexRay(TM) controller IP, optimized for the Xilinx(R) Automotive (XA) Spartan(TM)-3 generation devices.
  
  
• IP Cores, Inc. Announces three low-latency Fast Fourier Transform IP cores for SoC applications in the OFDM-based communications (WiMAX, MBOA, IEEE 802.11) and GPS fields (Tuesday Jun. 19, 2007)
  FFT64 core and two versions of FFT1024 are very compact and provide parameterized bit width with throughput of 1 sample per clock
  
  
• Jetstream Algorithms become NIST Certified and are now FIPS 140-2 Ready (Thursday Jun. 14, 2007)
  Jetstream Media Technologies announced today that the algorithms of its security IP cores have successfully passed the Cryptographic Algorithm Validation Program (CAVP), a strict governmental testing program for the validation of semiconductor algorithms
  
  
• IP Cores, Inc. Delivers a 10 Gbps AES-GCM FPGA Implementation (Tuesday Jun. 12, 2007)
  IP Cores, Inc. announces an FPGA implementation of the AES Galois/Counter Mode (GCM) supporting the IEEE 802.1ae standard with real-life throughput exceeding 10 Gbps for all Ethernet frame sizes.
  
  
• Sidense Qualifies 1T-Fuse(TM) in UMC's 130nm Process (Monday Jun. 11, 2007)
  By qualifying the NVM IP, a valuable memory addition to the foundry's IP Alliance Program, UMC's customers now have access to a low-cost, highly secure embedded NVM for applications such as electrical fuse replacement, flash and mask-programmable ROM replacement, code storage, RFID, unique ID, encryption, key storage, HDMI, and digital rights management (DRM).