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IP / SOC Products News

• Alma Technologies launches its new generation JPEG 2000 Encoder Core (Monday Jun. 11, 2007)
  Built on already-proven code, the new generation of the JPEG2k-E Encoder Core is a major advance that improves processing and makes it significantly easier to integrate JPEG 2000 in ASIC or FPGA-based systems.
  
  
• Digital Blocks Extends the DB9000 TFT LCD Controller IP Core Family with the availability of the DB9000AHB for the AMBA 2.0 Interconnect (Tuesday Jun. 05, 2007)
  The DB9000AHB IP Core targets systems-on-chip (SoC) ASSP, ASIC, and FPGA designs containing ARM embedded processors and the AMBA 2.0 AHB on-chip bus, as well as other processors that support the AHB bus, and system requirements for a TFT LCD panel
  
  
• CAST JPEG 2000 Encoder Core now Faster and More Capable (Monday Jun. 04, 2007)
  Second-generation core nearly doubles throughput speed and now integrates Tier-1 and Tier-2 functions to handle the biggest HDTV images without an external processor
  
  
• Lightspeed Logic collaborates with Cadence to deliver Reconfigurable Logic Reference Flow (Friday Jun. 01, 2007)
  Lightspeed Logic today announced immediate availability of the 65-nanometer Common Power Format (CPF)-enabled reference flow for Lightspeed Logic’s Reconfigurable Logic IP. This reference flow enables SOC designers to accelerate time-to-market for low-power designs using Lightspeed Logic’s Reconfigurable Logic IP.
  
  
• Chipidea's New USB PHY Architecture for 1.8V Devices Offers Industry's Lowest Power Consumption for SoC Designers (Friday Jun. 01, 2007)
  Chipidea, the world's leading provider of analog/mixed-signal subsystems and intellectual property (IP), today introduced a new generation USB physical layer architecture using 1.8V IO devices that offers the industry's lowest power consumption for System-on-Chip (SoC) designs in the 65nm and 45nm advanced technology nodes.
  
  
• CEVA Announces Next Generation CEVA-TeakLite-III DSP Architecture Featuring Native 32-Bit Processing (Thursday May. 31, 2007)
  Targeting next-generation Hi-Fi audio applications, the CEVA-TeakLite-III inherently supports 32-bit data processing functions with multiple precision points and offers an enlarged 64-bit data memory bandwidth. A FFT accelerator further boosts audio performance and reduces power consumption. For example, a 7.1 channel Dolby Digital Plus decoder would consume only 15% of the core's available MHz at a 90nm process, compared to 47% for its predecessor, the CEVA-TeakLite.
  
  
• Synopsys Announces the Industry's First Comprehensive SATA AHCI IP Solution (Wednesday May. 30, 2007)
  The DesignWare SATA AHCI core is compliant with the SATA 2.6 specification and AHCI 1.1 specification, and includes an ARM AMBA 2-compliant subsystem interface. The DesignWare SATA AHCI core has been verified against the industry-standard AHCI software drivers provided as part of the Linux® and Windows Vista™ operating systems.
  
  
• Denali Announces Databahn DDR3 Memory Controller IP Product (Tuesday May. 29, 2007)
  Denali's Databahn memory controller IP enables optimal performance for a wide range of DDR3 memory system applications including video and media processing, signal and network processing, and various consumer product applications.
  
  
• Silicon Image Intellectual Property Business Expands: HDMI Core IP Paired with PHY Semiconductors Solidifies Silicon Image's Industry Leadership (Tuesday May. 29, 2007)
  Silicon Image today announced that by combining its digital implementations of the HDMI IP cores with its HDMI analog physical layer (PHY) semiconductors, the company has begun to achieve significant market success, having already sold approximately four million HDMI PHY semiconductors.
  
  
• ASIC IP Announces Availability of its Serial ATA Controller Core (Tuesday May. 29, 2007)
  ASIC IP SATA Controller Core provides flexibility and ease in integration to customized software and both Host and Device applications. The SATA Core supports both Gen I and Gen II speeds
  
  
• Gaisler Research extends the GRLIB IP library with USB 2.0 Host Controller (Tuesday May. 29, 2007)
  The Host Controller supports High-, Full- and Low-Speed USB traffic. USB 2.0 High-Speed functionality is supplied by an enhanced host controller implementing the Enhanced Host Controller Interface (EHCI).
  
  
• PLDA Announces the Industry's First True Look at PCIe Gen 2 (Monday May. 28, 2007)
  The PLDA PCIe Gen 2 demo will include a FPGA-based board running PLDA's PCIe Gen 2 XpressRich IP on a server Platform featuring two quad processors from the industry leading processor manufacturer.
  
  
• Mentor Graphics Introduces Smallest Footprint, Industry-Compliant Serial ATA PHY for Optimized Low-Power Designs (Friday May. 25, 2007)
  The SATA PHY IP core, targeted for the TSMC 130nm Low Voltage Oxide (LVOD) process, provides a completely integrated solution for both SATA host and device applications running at either 1.5Gbps or 3.0Gbps speeds.
  
  
• Dolphin Integration launches a standard cell library with ultra-high density up to 30% savings (Friday May. 25, 2007)
  Immediately available at TSMC 180, and readily ported to other technological processes, SESAME uHDvLC benefits from a unique ''Try and Buy tutorial'' for guiding its evaluation.
  
  
• Synopsys Achieves Two IP Firsts: 65-nm PCIe and 90-nm USB Compliance Utilizing Common Platform Technologies (Thursday May. 24, 2007)
  Implemented in the 65-nanometer (nm) Common Platform process, Synopsys' DesignWare PHY for PCI Express and digital controllers are the first 65-nm IP to pass the PCI Express 1.1 compliance testing by the PCI-Special Interest Group (PCI-SIG(R)). Additionally, Synopsys' DesignWare USB 2.0 nanoPHY IP in the Common Platform 90-nm process is the first implementation to have earned Hi-Speed USB 'On-the-Go' (OTG) logo-certification by the USB Implementers Forum for devices manufactured at multiple foundries using a single GDSII source.
  
  
• MOSAID Introduces Industry's First Double Data Rate (DDR) SDRAM Physical Interface (PHY) Compiler (Tuesday May. 22, 2007)
  MOSAID's compiler automates the physical assembly of a DDR PHY by leveraging MOSAID's unique ''tiling'' approach to PHY construction where the individual components (tiles) of the PHY are connected by abutment. This method of connection eliminates extra wiring between PHY components, and ensures that the assembled PHY meets timing closure and other critical system requirements.
  
  
• Novelics Announces MemQuest, a Suite of Memory Compilers Built on a Common Platform that Concurrently Excels in Active Power, Leakage Current, Speed, Portability, and Cost (Tuesday May. 22, 2007)
  The MemQuest easy-to-use interface allows the System-on-Chip (SoC) designers (1) to explore their entire embedded memory subsystem based on memory types, user-definable operating conditions, area, power, density, speed, etc., on a block-by-block basis, (2) to choose the best optimized memory solution for each block, (3) to compile each memory block independently, (4) to generate all the required industry-standard front- and back-end views, and (5) to easily transfer the entire design files to their desired workstation, independent of the workstation’s operating system or hardware, all in a very short time
  
  
• CAST Releases DSP Coprocessor for Cortus APS 32-bit Processor Cores (Tuesday May. 22, 2007)
  Introduced a year ago, the APS family brings 32-bit processing power to designers more familiar with 8051s and other 8-bit microcontrollers. The new APS-DSP continues this approach, offering simple programming and adding fast math operations and optimized data handling to effectively support multimedia and other demanding analog or mixed-signal applications.
  
  
• MIPS Technologies Unveils Industry's First Fully Synthesizable Processors to Surpass 1 GHz; Broadcom Takes Early License (Tuesday May. 22, 2007)
  The MIPS32 74K cores are the industry's first fully synthesizable 32-bit processors to achieve operating frequencies greater than 1 GHz in TSMC 65nm process technology. Long-time MIPS licensee Broadcom Corporation was the first to license the 74K core in January as an early access customer—as the company continues to drive next-generation solutions for the business, consumer and service provider markets
  
  
• Silistix CHAINarchitect Bridges Gap Between Conventional and Leading-Edge Interconnect Methodologies (Monday May. 21, 2007)
  With CHAINarchitect, chip architects can easily explore new interconnect topologies and perform ''what if'' analyses to optimize on-chip communications (bandwidth and latency) between IP cores along with overall system characteristics such as power, die area, system-level performance and others.
  
  
• Denali and LeCroy Demonstrate Industry-Leading PCIe 2.0 Solutions at PCI-SIG Developers' Conference (Monday May. 21, 2007)
  LeCroy's Protocol Analyzer and new x16 Gen2 Interposer Card coupled with Denali's proven design and verification IP tools provides an integrated and pre-tested solution that speeds customers' adoption of PCIe 2.0.
  
  
• Algotronix to demonstrate its DesignTag Electronic IP labelling technology at the 44th DAC in San Diego (Friday May. 18, 2007)
  Based on cryptographic research into ''side channels'' DesignTag is a small, low power, active digital circuit supplied as an IP core for inclusion in larger designs. The presence of DesignTags can be detected by a sensor placed in contact with the package of the chip which contains them. DesignTag communicates a unique tag to the sensor which can then be used to access information on the tagged product in a web-based database.
  
  
• Synopsys Switch IP for PCI Express Passes PCI-SIG Compliance Testing (Thursday May. 17, 2007)
  The DesignWare Switch IP for PCI Express is used to power Agilent Technologies' Protocol Test Card (PTC), one of three ''Gold Tests'' required by PCI-SIG for products to achieve compliance and be listed on PCI-SIG's Integrators List.
  
  
• Denali Announces Availability of PCI Express I/O Virtualization Solutions (Thursday May. 17, 2007)
  Denali's Databahn PCIe IOV cores and PureSpec PCIe verification IP products provide full support of the Address Translation Service specification, Single-Root I/O Virtualization specification, including physical and virtual function (VF) configuration spaces, VF Alternate Routing-ID, and Functional Level Reset (FLR) capabilities.
  
  
• Tensilica Announces Industry's First MP3 Decoder Under 6 MHz (Wednesday May. 16, 2007)
  This MP3 decoder now runs at the lowest power and is the most efficient in the industry, requiring just 5.7 MHz when running at 128Kbps, 44.1 KHz and dissipating 0.45 mW in TSMC’s 65nm LP process (including memories).
  
  
• Synopsys Unveils Industry's First Certified Hi-Speed USB 'On-the-Go' nanoPHY IP for TSMC'S 65-Nanometer Process (Tuesday May. 15, 2007)
  Synopsys' industry-leading USB 2.0 nanoPHY mixed-signal IP, now available in the TSMC 65-nm process nodes, uses half the power and die area compared to previous USB solutions and enables faster time-to-market and reduced risk.
  
  
• Cebatech Announces GZIP Family of CebaIP Cores for Efficient High Speed Compression and Decompression inside Data and Storage Networking ASICs and FPGAs (Tuesday May. 15, 2007)
  The GZIP family of cores is based on CebaTech's integrated CebaIP Platform. The CebaIP platform provides a modular approach to offering IP cores, enabling design engineers to quickly and easily integrate each configuration into their ASICs or FPGAs.
  
  
• Faraday Introduces Repairable Memory Development System - REMEDE (Tuesday May. 15, 2007)
  The fully integrated embedded memory system is comprised of Built-in-Self-Repair (BISR) function and the fuse group. Faraday's REMEDE™ in UMC 0.13um is available now; the one in 90nm will be ready in Q3' 07, and in 65nm will be ready by Q4' 07.
  
  
• Cadence Selects Wipro-NewLogic's Wireless LAN IP for its Low-Power Methodology Kit (Tuesday May. 15, 2007)
  Cadence Design Systems has chosen Wipro-NewLogic to license Wipro-NewLogic's IEEE 802.11 a/b/g MAC and Modem for integration into its Low-Power Methodology Kit
  
  
• License-free, FPGA-based Single Chip Controller for Low Cost SERCOS III I/Os available (Monday May. 14, 2007)
  SERCOS International has introduced Easy-I/O, a free IP core software for low-cost FPGA chips, which allows SERCOS III to be integrated into basic I/O slave devices with minimal development and integration effort