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IP / SOC Products News

• Microtronix premieres this summers' Full HDTV ''Streaming'' Blockbuster Hit (Monday May. 14, 2007)
  Full HDTV (1080p) consumer electronics, video conversion / enhancement equipment, military vision systems, medical imaging, data networking, Ethernet, PCIe, handheld video devices and data recorders requiring high-performance memory subsystems are now taking advantage of the latest ''Streaming'' Multi-port SDRAM Memory Controller IP Core available from Microtronix.
  
  
• Duolog Technologies tapes out IEEE 802.15.4/Zigbee radio which offers significant time to market reductions for semiconductor customers (Thursday May. 10, 2007)
  Duolog Technologies today announced the tape-out of a 0.13um IEEE 802.15.4/Zigbee radio test chip as part of their 802.15.4 transceiver development program.
  
  
• Intrinsity's FastCore(TM) Embedded ARM, MIPS and PowerPC Cores Offer 2 to 4X Better Performance (Wednesday May. 09, 2007)
  Built using Intrinsity's proprietary Fast14® technology, RTL FastCore embedded cores are cycle-accurate, drop-in replacements that double the performance of existing embedded processor cores, while preserving the same application software and test infrastructure as the original core and occupying approximately the same silicon area.
  
  
• Lightspeed Logic Introduces Reconfigurable Logic for TSMC 90nm with ARM Standard Cell Libraries (Wednesday May. 09, 2007)
  Lightspeed Logic's Reconfigurable Logic delivers a density and performance breakthrough for mask reconfigurable solutions, achieving 80% the density of traditional methodologies for multi-million gate logic blocks, twice the density of competing mask reconfigurable solutions.
  
  
• Silicon Hive Announces HiveFlex VSP2200 Series Processor Cores for HD Video Signal Processing (Wednesday May. 09, 2007)
  The HiveFlex VSP2200 Series targets HD widescreen TVs with high quality video displays. The HiveFlex VSP 2200 series is built upon a tiled architecture. A tile is fully programmable and can support various video processing algorithms, including, image stabilization, codecs, de-interlacing, picture rate up-conversion, spatial scaling, etc., for displays up to HD (1920 x 1080) and beyond.
  
  
• DOLPHIN Integration releases a ROM in 65 nm with Ultra high density and ultra low leakage (Wednesday May. 09, 2007)
  Typically, the silicon area of a 6-Mbit instance in 65 nm will decrease as far as 0.63 mm2 with only 1.2 uA leakage current,and the same 6-Mbit instance in 90 nm will be as low as 0.95 mm2 with only 1.8 uA leakage current.
  
  
• MOSAID Introduces Breakthrough Flash Memory Architecture (Monday May. 07, 2007)
  HLNAND Flash is a high-performance solution that combines MOSAID's own HyperLink memory technology with industry standard NAND Flash cell technology to deliver the industry's most advanced feature set, reaching sustained I/O bandwidths more than ten times higher than conventional Flash
  
  
• STMicroelectronics Samples 65nm Multi-Standard Hard Disk Drive Physical Layer IP (Wednesday May. 02, 2007)
  STMicroelectronics today revealed the industry's first successful fabrication of the next- generation 65nm serial-interface MIPHY (Multi Interface PHY) Physical Layer interface IP (Intellectual Property). ST designed the macro-cell to be integrated with other functions into low power System-on-Chip (SoC) devices supporting both 3 Gbps and 6 Gbps Serial ATA (SATA) hard disk drives (HDDs) for mobile and desktop computing applications.
  
  
• MoreThanIP First to Demonstrate 2.5 Gigabit Interoperability with Broadcom Switch (Tuesday May. 01, 2007)
  MoreThanIP today announced that it is the first third-party intellectual property (IP) vendor to achieve interoperability with the Broadcom StrataXGS III BCM56580 2.5 Gigabit switch. This solution expands the ecosystem for 2.5 Gigabit applications and enables designers to rapidly develop high-performance, end-to-end applications for communications systems with Broadcom switches using Altera Stratix II GX FPGAs, structured ASICs or standard cell ASICs.
  
  
• Tensilica Offers Dolby Digital Plus 7.1-Channel Decoder for HD DVD Players, Blu-ray Disc Players, and Set-Top Boxes (Tuesday May. 01, 2007)
  Tensilica today announced that it will deliver a Dolby Digital Plus 7.1-channel decoder designed for HD DVD players, Blu-ray Disc players, and set-top boxes. Tensilica will also offer a Dolby Digital Plus 5.1-channel decoder/converter to ensure compatibility with most existing home theater systems equipped with coaxial or optical digital audio inputs.
  
  
• Inapac Technology Releases New 16Mb DRAM Design for Mobile Applications That Reduces SiP/MCP Cost (Thursday Apr. 26, 2007)
  Inapac's SiPFLOW platform is licensed to SiP and MCP suppliers addressing such applications as feature-rich cellular handsets, personal media players and LCD-based displays.
  
  
• Synopsys Releases Wireless USB WHCI Host and Dual-Role Device IP Based on the Certified Wireless USB Specification From USB-IF (Thursday Apr. 26, 2007)
  Designed for applications like PC chipsets, set top boxes, personal video recorders, DVD Players and digital TVs, the DesignWare Wireless USB Host is based on the Wireless Host Controller Interface (WHCI) specification. Designing to the WHCI specification enables system makers to build applications on standard WHCI drivers to save months of software driver development.
  
  
• CebaTech Announces CebaIP Platform for End-to-End Development of Data and Storage Networking ASICs or FPGAs (Thursday Apr. 26, 2007)
  The CebaIP platform is a protocol-complete hardware and software framework for developing end-to-end data and storage networking solutions. Using the CebaIP Platform's integrated advanced direct memory access (DMA) controller with the OpenBSD software driver, designers are able to rapidly achieve complete data networking and storage product solutions.
  
  
• Synopsys Enhances DesignWare Synthesizable IP for AMBA 2 and AMBA 3 AXI Protocols (Wednesday Apr. 25, 2007)
  The new release includes a new I2S protocol IP for the APB bus, an AXI-to-APB3 compliant bridge with built-in fabric, and a highly configurable AXI-to-AXI bridge supporting a multi-layered AXI bus-based design. The release also includes extensive enhancements to the existing IP for the AMBA 2 and AMBA 3 AXI protocols
  
  
• Xelic Announces Immediate Availability of 10Gb/s Ethernet Rate Adaptation IP Core (Wednesday Apr. 25, 2007)
  The XCE10GA performs rate adaptation through the insertion and removal of complete PCS blocks containing idle characters to provide maximum transparency capability. Optional flow control is provided through the insertion of programmable PAUSE frames in open or closed loop configurations
  
  
• Impinj's AEON/MTP Logic Nonvolatile Memory IP Earns TSMC Quality Certification (Monday Apr. 23, 2007)
  The AEON/MTP Parallel Architecture core achieved silicon validation in TSMC's 0.18-micron process and is the first NVM multiple-time-programmable (MTP) IP product to meet the foundry's reliability, performance and manufacturing standards.
  
  
• S1 Core, a 64-bit Wishbone-compliant CPU Core based upon the OpenSPARC T1 microprocessor, easily synthesized for Virtex-4 (Monday Apr. 23, 2007)
  Arturo Mann proudly announces that he has successfully synthesized the S1 Core on a Xilinx Virtex-4 FPGA device.
  
  
• Jetstream Media Technologies' New Real-Time Video Effect IP Core Delivers Easy to Use, Fun and Personalized Memories (Wednesday Apr. 18, 2007)
  JetFx-3000 consists of three components: the industry’s most advanced real time video effect silicon IP core, engineered for resolutions up to HD quality; the embedded sequencer software; an optional composer software
  
  
• Xilinx and 4i2i demonstrate H.264 HD encoder and decoder with streaming over RTP (Tuesday Apr. 17, 2007)
  Xilinx and 4i2i today announced one of the world’s first demonstration of an FPGA-based real-time H.264 main profile video encoder, coupled with a high profile video decoder, with streaming over RTP
  
  
• Mixel Announces the Availability of Its 4.25 Gbps High Performance, Highly Programmable, SerDes IP's Characterization Report (Tuesday Apr. 17, 2007)
  The MXL-SRDS-4254 is a high performance quad SerDes IP with the highest programmability available on the market. It is targeted for a broad range of serial interface standards. This high performance, low power IP has four channels, each running at 1 to 4.25 Gbps. The IP is silicon-proven in TSMC and Chartered 130nm process technologies. The extensive characterization report is now available.
  
  
• Handshake Solutions releases clockless interconnect IP (Tuesday Apr. 17, 2007)
  This scan-testable interconnect IP allows designers to exploit the benefits of clockless design, such as low power consumption and low Electromagnetic Interference (EMI), across a complete sub-system. Compatible with clocked and clockless masters and slaves, the multilayer AHB simplifies timing closure while retaining flexibility of design.
  
  
• CAST Expands Image Compression Line with New JPEG-LS Encoder Core (Monday Apr. 16, 2007)
  Semiconductor intellectual property (IP) provider CAST, Inc. today announced that it has expanded its family of image compression IP products with a new lossless compression core using the JPEG-LS standard.
  
  
• MOSAID Delivers Silicon-Proven PLLs at 65 Nanometers (Tuesday Apr. 10, 2007)
  MOSAID's fractional-N PLL is a fully integrated, programmable, low-power, high-performance Delta-Sigma, Fractional-N product. It is optimized for line-operated and battery powered applications at system clock rates as high as 3.2GHz. The large fractional multiplication range of MOSAID's PLL enables it to address many markets and applications with a single, low-cost crystal frequency, thus reducing inventory, delivery time and bill of materials (BOM) cost.
  
  
• Uniquify Releases Industry's First Smart DDR Memory Controllers (Tuesday Apr. 10, 2007)
  Uniquify's DDR2 and mobile DDR memory controller IP are complete DDR SDRAM solutions incorporating a compact, highly configurable memory controller and PHY macro compiler to resolve tough timing problems such as data/clock skew, setup/hold time, and complex physical implementation issues
  
  
• Impinj First and Only Provider of One-Time- and Multiple-Time-Programmable Nonvolatile Memory Cores in 90-nanometer Logic CMOS (Thursday Apr. 05, 2007)
  Impinj's AEON NVM cores enable the integration of both high-density OTP NVM and MTP NVM into system-chips for greater design flexibility and performance. Leveraging Impinj's proprietary floating-gate technology, AEON NVM cores provide an alternative to costly embedded Flash memory and cumbersome off-chip EEPROM.
  
  
• TranSwitch Announces Optimized Ethernet Gigabit PHY IP Core (Thursday Apr. 05, 2007)
  TranSwitch's IP core supports 10Base-T, 100Base-TX and 1000Base-T. TranSwitch obtained the Gigabit technology when they acquired Mysticom Ltd., the largest provider of 10/100Base-T IP cores.
  
  
• S3 Mixed Signal IP Portfolio Tapes Out at 65nm (Thursday Apr. 05, 2007)
  S3 (Silicon and Software Systems) today announced the tape-out at 65nm of its high-performance mixed signal IP portfolio for wireless and consumer applications. S3 has already achieved multiple volume engagements with its first-time right silicon at 90nm, enabling rapid time to production revenue for its global client base.
  
  
• Virage Logic First Semiconductor IP Vendor With Silicon Proven Memory on TSMC's 65nm GP Process (Thursday Apr. 05, 2007)
  Virage Logic's robust and production-tested High-Density (HD) SRAM meets the stringent density, performance and leakage requirements of System-on-Chip (SoC) designers moving to 65nm, allowing them to capitalize on the cost advantages they seek at advanced process nodes.
  
  
• Ittiam Systems Gets the Coveted 'Wi-Fi CERTIFIED(TM)' for its 802.11g IP (Wednesday Apr. 04, 2007)
  Ittiam Systems today announced that it has achieved the most well known ''Wi-Fi Certification'' from the Wi-Fi Alliance(R) for IEEE 802.11b, IEEE 802.11g, WPA(TM), WPA2(TM) and EAP for its WLAN IP.
  
  
• Altera's Triple-Speed Ethernet MegaCore Function Successfully Completes UNH-IOL Conformance Testing (Tuesday Apr. 03, 2007)
  In addition to the MAC and 1000 BASE-X PCS test suites, the Triple-Speed Ethernet MegaCore function, implemented on Stratix II and Stratix II GX devices, passed the independent lab's point-to-point interoperability, auto-negotiation and flow control test suites.