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IP / SOC Products News

• RFEL's Mixed Radix cores, adaptable for next generation 3GPP LTE base station applications (Tuesday Apr. 03, 2007)
  The exact specifications for 3GPP LTE have yet to be ratified, but it's been clear for sometime that mixed radix FFTs will form a fundamental element of the design, and so putting RFEL in a leadership position of being able to provide solutions immediately from its portfolio of licensable IP.
  
  
• MindTree Consulting Announces ''UltraWiz'' range of UWB IP's (Tuesday Apr. 03, 2007)
  MindTree's ''UltraWiz'' UWB MAC silicon IP is based on the WiMedia MAC 1.0 specification and MAC-PHY interface specification V1.2 and has been validated on FPGA platform. The ''UltraWiz'' IP meets all mandatory and optional features and is ready for integration in a SOC platform. In addition, MindTree offers complementary test tool ''UTest'' for validation and testing of all mandatory and advanced features.
  
  
• Freescale Opens Licensing of Power Architecture(TM) e200 Core Family Through IPextreme (Monday Apr. 02, 2007)
  Extending the reach of Power Architecture(TM) technology in the embedded market, Freescale Semiconductor is licensing its e200 core family to designers of system-on-chip (SoC) devices and application-specific semiconductor products (ASSPs). Freescale will license its e200 cores through an agreement with semiconductor intellectual property (IP) licensing specialist IPextreme Inc.
  
  
• Faraday Implements Ultra Small ARM926EJ-S Hard Core in UMC 0.13um Process (Monday Apr. 02, 2007)
  Faraday Technology today announced that it has implemented the ARM926EJ-S hard core in UMC 0.13um process. The hard cores of ARM926EJ-S in UMC 0.13um is available now, and the 90nm hard cores will be ready in Q2 2007.
  
  
• Dolphin Integration releases its RAM for 90 nm nodes with dual optimization: for ultra-low power and for extremely high density (Friday Mar. 30, 2007)
  Dolphin Integration, the Enabler of mixed signal SoCs, has released its RAM for 90 nm nodes with dual optimization: for ultra-low power and for extremely high density
  
  
• Virage Logic Adds Liberty Composite Current Source Model Support to Memory and Logic IP (Thursday Mar. 29, 2007)
  Used in conjunction with the Synopsys Galaxy(TM) Design Platform, the high-accuracy CCS timing and noise models allow the designer to reduce guard-band margins during design implementation and sign-off, thus improving design performance and reducing design iterations.
  
  
• Impinj Announces Semiconductor Industry's First Multi-Time-Programmable Nonvolatile Memory IP Qualified in 90 nm Process Technology (Wednesday Mar. 28, 2007)
  The first-ever multiple-time-programmable (MTP) NVM IP qualified and released for production at the 90-nanometer process node, Impinj's AEON/MTP cores provide the cost, power and functionality benefits of embedded NVM in standard logic CMOS (also known as Logic NVM.)
  
  
• CEVA's Fully Programmable Mobile Multimedia Solution Passes Allegro H.264 Test Suite (Wednesday Mar. 28, 2007)
  CEVA and Allegro today announced that CEVA's MM2000(TM) programmable multimedia platform has passed the Allegro test suite for H.264 Baseline Profile Levels 2 and 3, including Syntax and Stress tests.
  
  
• Mentor Graphics Announces Subsystem Intellectual Property Launch with First Delivery of Integrated USB Solution (Monday Mar. 26, 2007)
  Mentor Graphics today announced a technology launch of subsystem intellectual property (IP), beginning with the industry's first USB subsystem solution from a single-source EDA provider. Mentor Graphics is the only EDA company that develops its own digital controller, hardware PHY (physical layer), and embedded software IP to deliver an integrated and verified IP solution for today's complex electronics designs.
  
  
• MoSys Launches New Memory Macros Specifically Configured for Mobile Handset Displays (Thursday Mar. 22, 2007)
  Compatible with high-volume processes at major foundries and integrated device manufacturers, the MoSys 1T-SRAM Dual-Port Display macro uses standard foundry process technologies and offers a reduction in overall silicon area of up to 70 percent when compared to conventional embedded memory solutions.
  
  
• Silterra and Novelics Demonstrate Low Power coolSRAM-1T(TM) (Tuesday Mar. 20, 2007)
  Based on Novelics' patented memory architecture, coolSRAM-1T is a complete memory sub-system that includes the cell arrays, associated logic, and self-refresh circuitries, making it a simple drop-in solution. coolSRAM-1T is based on standard CMOS process technology and requires no extra mask layers or doping.
  
  
• Jetstream Media Technologies Delivers Three New IP Cores - A Scalable Modular Exponentiation Accelerator and OC-192-Data-Rate XTS/Combo IP Cores (Tuesday Mar. 20, 2007)
  Jetstream Media Technologies announced today the availability of three IP cores: modular exponentiation accelerator, ultra fast XTS IP, and ultra-fast dual-mode JetCombo-2 IP.
  
  
• ARM Extends Cortex Family with First Processor Optimized for FPGA (Monday Mar. 19, 2007)
  The ARM Cortex-M1 processor extends the range of the ARM Cortex processor family and enables OEMs to standardize around a common architecture across the performance spectrum. Actel has worked with ARM as lead Partner and is the first licensee of the Cortex-M1 processor for use by their FPGA customers
  
  
• CEVA Unveils New Family of Multimedia Solutions for High Volume, Low Cost Mobile Consumer Electronics (Monday Mar. 19, 2007)
  Building on CEVA's established Mobile-Media(TM) architecture, the Mobile-Media-Lite(TM) family offers a complete feature set for a range of applications such as MobileTV Players, entry-level Portable Media players (PMPs) and multimedia phones.
  
  
• Impinj Delivers Logic Nonvolatile Memory in Tower Semiconductor's 0.13-Micron Process (Monday Mar. 19, 2007)
  Ideal for portable applications, the certified AEON/MTP Parallel Architecture NVM IP consists of hard macro cores in 8-bit to 256-bit configurations with parallel data output enabling instant access to all data bits. Additional features include 10-year data retention, capability for up to 15,000 write/erase cycles and on-chip high-voltage circuitry for simplified in-field programming.
  
  
• Avalon Microelectronics Announces Availability of 40G SONET/SDH Framer/Mapper/Pointer Processor (Monday Mar. 19, 2007)
  Avalon Microelectronics today announced the first commercially available FPGA-based integrated SFI-5 core and 40G SONET/SDH framer / pointer processor. The Athabasca is ideally suited for FPGA-based designs and, as a standard product, can greatly reduce development time and costs for customers developing SONET/SDH systems.
  
  
• Faraday Launches FIE7020 Audio Platform Solution Targeting Portable Audio Applications (Wednesday Mar. 14, 2007)
  Faraday provides high performance 32-bit RISC CPU-based audio solutions, FIE7020 platform, which supports NAND flash/SD MMC card/HDD-based audio solutions with add-on video playback functions.
  
  
• SNOWBUSH Announces Silicon-Proven SerDes IP in TSMC 65nm G+ Process for PCI Express, SATA & Other Serial Standards (Tuesday Mar. 13, 2007)
  SNOWBUSH's 1.0-5.0Gbps multi-standard SerDes macro provides a complete physical media attachment layer for PCI Express, SATA, SAS and Fibre Channel serial interconnects, and supports XAUI, Rapid I/O, Gigabit Ethernet and Infiniband.
  
  
• Lattice Announces Industry's Fastest Low-Cost FPGA DDR2 Controller (Monday Mar. 12, 2007)
  Lattice Semiconductor today announced the immediate availability of the industry's first 533 Mbps Double Data Rate 2 (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) controller Intellectual Property (IP) core supporting a Low-Cost Field Programmable Gate Array (FPGA) family. This DDR2 SDRAM IP core is optimized for Lattice's award winning LatticeECP2 and LatticeECP2M LatticeSC Extreme Performance FPGA family.
  
  
• Techno Mathematical rolls IP for one-chip, full-HD codec (Friday Mar. 09, 2007)
  Techno Mathematical Co. Ltd. has developed the industry's first H.264/MPEG-4 intellectual-property core to offer a one-chip encoder/decoder LSI solution. The High Profile core features high-definition (1920 x 1080i) image compression and decompression.
  
  
• Arasan Chip Systems Launches Industry's First Suite of MIPI IP Cores (Thursday Mar. 08, 2007)
  The new products available include the Display Serial Interface (DSI) IP Core, the Camera Serial Interface (CSI-2) IP Core, and the D-PHY IP Core. The SLIMbus(TM) IP Core (Serial Low-power Inter-chip Media bus) supporting the preliminary draft specification is also available.
  
  
• CEVA Extends Connectivity Product Line With Bluetooth 2.0+EDR (Thursday Mar. 08, 2007)
  CEVA today unveiled a new platform solution for Bluetooth Specification Version 2.0 + EDR, providing Enhanced Data Rate (EDR) performance to chip designers looking to embed Bluetooth in consumer or automotive integrated circuits. Leveraging on the Company's silicon-proven and fully certified Bluetooth 1.2 solution, CEVA's low power Bluetooth 2.0+EDR IP provides full flexibility in the choice of CPU, Bluetooth radio chipset and operating system.
  
  
• Tundra Semiconductor Offers RapidIO Endpoint IP (Wednesday Mar. 07, 2007)
  The Endpoint IP enables high performance Serial RapidIO system interconnect between processors, bridges, remote memories, customer defined endpoint devices and Tundra RapidIO switches. The IP is compliant with RapidIO Interconnect Specification (Revision1.3) and supports up to 10 Gbps payload. Fully synthesizable, the IP is designed to be combined with technology specific SerDes on multiple process technologies.
  
  
• SNOWBUSH microelectronics announces availability of silicon verified, 80nm, Line-Lock PLL IP Block (Tuesday Mar. 06, 2007)
  This synthesizer is in high volume production and has been implemented in a wide variety of technology nodes including 150, 130, 90, 80 and 65nm. It has been optimized for excellent power-supply rejection, temperature stability and extremely low jitter. It features a high resolution, 20-bit, noise shaping filter that provides fine-frequency tuning.
  
  
• Arasan Chip Systems Extends USB IP Offerings to Actel's CompanionCore Program (Tuesday Mar. 06, 2007)
  Arasan has optimized its USB 2.0 Host, USB 2.0 Hub, USB 2.0 Device and USB OTG IP cores for use with Actel's flash-based, single-chip Actel Fusion, IGLOO, ProASIC3/E and ProASIC Plus field-programmable gate arrays (FPGAs).
  
  
• Lattice Announces LatticeECP2M FPGA Solution for PCI Express V1.1 (Monday Mar. 05, 2007)
  LatticeECP2M PCI Express Core Successfully Tested Against PCI Express Version 1.1 Specifications; Solution Enables Single-Chip, Programmable PCI Express Endpoints
  
  
• DOLPHIN Integration announces a new generation of Audio CODEC with embedded voltage regulator (Thursday Mar. 01, 2007)
  Dolphin Integration has just released a Second Generation of audio CODECs offering a wide set of features and lowering integration costs. With an SNR at system-level measured at 90 dB, Dolphin's CODEC Best-in-class audio quality was already preferred by diverse Golden Ears finding it at par with the top external codec IC's
  
  
• CAST PCI Express Core Achieves PCI-SIG Certification (Wednesday Feb. 28, 2007)
  The CPXP-EP core implements the transaction, data link, and physical protocol layers in compliance with the 1.0a PCI Express Base Specification, and provides an efficient x1 single-lane device link for bidirectional data transfer rates up to 250 MB/s. Extra features for error checking, configuration flexibility, and power saving are all included.
  
  
• Analysis: BDTI Certifies ARC's H.264 Performance (Wednesday Feb. 28, 2007)
  This month BDTI and silicon intellectual property licensor ARC International announced completion of BDTI Solution Certification™ of the H.264 decode performance of the ARC Video Subsystem. The ARC Video Subsystem, the first product to be certified under BDTI's Solution Certification Service, is a programmable subsystem capable of supporting multiple video standards.
  
  
• Kaben Developing FM Tuner IP (Tuesday Feb. 27, 2007)
  Kaben's FM Tuner IP significantly reduces the manufacturer's complexity of integrating a high quality FM tuner functionality into their products. Applications for the FM Tuner IP are cellular phones, MP3 players, Personal Digital Assistants, portable audio devices, portable gaming devices and portable GPS receivers. The IP block is designed for a pure CMOS process and can be integrated into any customer's mixed-signal or digital chips.