English
| |
-
OneSpin Solutions Announces Customizable Integration Between 360 MV Verification Solution and Platform LSF Infrastructure (Monday Feb. 22, 2010)
OneSpin Solutions today announced the customizable integration between OneSpin’s 360 MV formal assertion-based verification (ABV) solution and Platform Computing’s LSF infrastructure, the industry’s leading workload management solution for high-performance computing environments.
-
Jasper Releases New Formal Verification Proof Kits For LPDDR1, LPDDR2 and DDR3 (Monday Feb. 22, 2010)
Jasper Design Automation, provider of advanced formal technology solutions, today announced the availability of Proof Kits for LPDDR1 and LPDDR2, and DDR3 SDRAM. These Jasper Proof Kits are sets of properties, written in SystemVerilog, related to standard JEDEC interface protocols.
-
Open Virtual Platforms (OVP) Initiative Releases High Performance Models of Advanced MIPS Technologies Processors (Wednesday Feb. 17, 2010)
The Open Virtual Platforms (OVP) initiative has released new models of MIPS Technologies, Inc. processor cores and continues its move to becoming the de facto source of fast models.
-
CoWare Releases Renesas' SH-4A Core Model and Reference Virtual Platform for Automotive, Consumer and Wireless Designs (Tuesday Feb. 16, 2010)
CoWare today announced the availability of the high-speed model for Renesas Technology's (Renesas) SH-4A core model. The model is already in use at Renesas for the creation of high-speed virtual platforms targeted at Renesas customers in the automotive, consumer and wireless markets
-
Carbon Design Systems, VeriSilicon Form IP partnership (Thursday Feb. 11, 2010)
Carbon Design Systems and VeriSilicon announced today that they have partnered to integrate VeriSilicon’s ZSP® models into the Carbon SoC Designer virtual platform.
-
Bluespec Delivers Plug-and-Play Library for Algorithm and Datapath Design (Tuesday Feb. 09, 2010)
Bluespec Inc. today announced its Pipelined Architecture Composers library (PAClib), the industry’s first parameterized, plug-and-play building block library for specifying, modeling and synthesizing algorithm and datapath designs.
-
CoWare Teams with Xilinx to Accelerate LTE Basestation Design (Monday Feb. 08, 2010)
CoWare has signed a distribution agreement with Xilinx. Under the agreement, CoWare has integrated and is distributing models of Xilinx’s LTE Baseband IP portfolio with its SPW LTE solution.
-
Paradigm Works Releases Free Open Source Software for VMM-based Verification (Monday Feb. 08, 2010)
Paradigm Works announced today that it has released its RegWorks™ Spec2Reg tool as Free Open Source Software (FOSS) for the chip development community. Built on VMM's Register Abstraction Layer (RAL) capability, Spec2Reg provides development teams a fully automated path for taking register definitions from design specification to verification implementation.
-
SpringSoft Simplifies Verification of Low-power Chips with Advanced Power-aware Debug Solution (Monday Feb. 08, 2010)
SpringSoft today introduced a new power-aware debug module for its award-winning Verdi Automated Debug System. Power-aware debug accelerates the comprehension of power intent and automates the process of visualizing, tracing and analyzing the source of power-related errors.
-
Mixel Achieves Full-Chip Verification of a Programmable 3.2Gbps Quad Transceiver IP with Infinisim RASER (Tuesday Feb. 02, 2010)
Infinisim Inc. announced today that Mixel®, a leading provider of silicon-proven mixed-signal Intellectual Property (IP) cores, used Infinisim’s RASER mixed-signal simulator to verify the functionality of a programmable 3.2Gbps quad-lane SerDes chip, demonstrating RASER’s unprecedented capacity and accuracy to handle a full-chip mixed-signal design.
-
Virage Logic's 45nm and 28nm SiWare Memory Compilers Automatically Support Calypto's PowerPro MG tool (Monday Feb. 01, 2010)
Calypto Design Systems today announced that Virage Logic’s 45-nanometer (nm) and 28nm SiWare™ Memory compilers now automatically generate PowerPro® MG power optimization models for reducing System-on-Chip (SoC) embedded memory power.
-
Agnisys announces support for OVM Register Package in IDesignSpec (Friday Jan. 29, 2010)
Agnisys today announced the immediate availability of IDesignSpec with support for the OVM Register Package. This comes close on heels of the news on the OVM Register Package 1.0 from Mentor Graphics.
-
OCP-IP Delivers Even More OSCI TLM 2.0 Compatibility in Advanced SystemC TLM Kit (Wednesday Jan. 27, 2010)
OCP-IP today announced the availability of version 2.2x2.1 of the OCP Modeling Kit. The new version is compatible with OSCI’s TLM 2.0.1, the most recent version of TLM 2.
-
Renesas Adopts Cadence Virtuoso Technology for Mixed-Signal and Analog Design at its Global Design Centers (Tuesday Jan. 26, 2010)
Cadence today announced that Renesas has upgraded to the latest version of Cadence® Virtuoso® technology at its global design centers.
-
Mentor Graphics Catapult C Adds SystemC Synthesis and Expands Full-Chip Capabilities (Monday Jan. 25, 2010)
Catapult C support for SystemC source descriptions augments its existing support for ANSI C++ input, allowing high-level synthesis users to choose the industry standard high-level synthesis language that best suits their company’s methodology.
-
Cadence OVM SystemVerilog Solution Enables More Thorough Verification and Reduces Costs at Mitsubishi Electric (Monday Jan. 25, 2010)
By deploying the Cadence OVM SystemVerilog module-based solution, Mitsubishi has been able to conduct more thorough verification on its chips while reducing costs.
-
Toshiba Information Systems (Japan) Standardizes on VMM-LP Low Power Verification Methodology (Monday Jan. 25, 2010)
Toshiba Information Systems (Japan) used Synopsys' voltage-aware VCS® functional verification solution with MVSIM and VMM-LP to deploy a uniform, structured and repeatable verification methodology across its low power design projects.
-
BDTI Certified Results Show PICO High Level Synthesis Platform Produces Quality of Results Comparable to Hand-coded RTL (Tuesday Jan. 19, 2010)
The PICO High Level Synthesis Platform from Synfora has achieved certification in BDTI’s new High-Level Synthesis Tool Certification Program™. An FPGA-based implementation of a complex video motion analysis algorithm (the BDTI Optical Flow™ application) using PICO C synthesis tools outperformed a traditional DSP processor implementation on throughput by a factor over 40x achieving a processing rate of 204 frames per second and provided a 30X price/performance advantage over DSPs.
-
Mentor Graphics Delivers Hardware-assisted Solution for the Accelerated Verification of USB 2.0 Products (Thursday Jan. 14, 2010)
Mentor Graphics today announced a hardware-assisted solution to accelerate the verification of Universal Serial Bus (USB) 2.0 products, including hard disk drives and other mass storage devices.
-
Freescale Semiconductor Collaborates with Mentor Graphics on Tessent Silicon Test, Yield Analysis, Calibre Physical Verification and DFM (Monday Jan. 11, 2010)
Mentor Graphics today announced that Freescale Semiconductor has selected Mentor as an ideal partner in the silicon test, yield analysis, physical verification and DFM technology areas.
-
Synopsys Speeds Timing Signoff by 2X With Latest Multicore Technology (Monday Jan. 11, 2010)
With this latest addition, Synopsys' PrimeTime tool provides a new level of flexibility - enabling design teams to achieve optimal runtime performance across their heterogeneous multicore compute environments by utilizing distributed and threaded multicore processing in tandem.
-
Aldec(R) Releases RTL Simulator with Enhanced Assertions and Xilinx(R) SecureIP Support (Monday Dec. 21, 2009)
Aldec releases its latest RTL and gate-level simulator, Active-HDL™ 8.2 sp1, for FPGA design and verification engineers. Active-HDL 8.2 sp1 includes full support for Xilinx® SecureIP, IEEE VHDL/Verilog® encrypted IP and an enhanced Assertions bundle option.
-
Magma Announces SiliconSmart ACE -- New Standard in IP Characterization for 28 nm and Below (Monday Dec. 14, 2009)
By leveraging new Accelerated Circuit Engine (ACE) technology and embedding Magma's ultra-fast FineSim(TM) SPICE simulator, the fully automated SiliconSmart ACE flow delivers more accurate models and faster turnaround time than other tools, setting a new standard in IP characterization and modeling for designs targeted at 28-nanometer (nm) and smaller process nodes.
-
Sigasi Announces Production Release and Pricing for its IDE for VHDL (Friday Dec. 11, 2009)
Sigasi today announced the first production release and pricing for Sigasi HDT, an Intelligent Development Environment (IDE) for VHDL.
-
DOLPHIN Integration moving ahead towards Assertion-Based Verification with SLASH (Friday Dec. 11, 2009)
With the autumn 2009 releases of SLASH, DOLPHIN Integration is delivering a significant upgrade for automating specification-based design verification techniques. Indeed, the bundle SLASH - schematic editor SLED coupled with mixed signal simulator SMASH – now natively supports Property Specification Language (PSL) assertions to empower designers for performing Assertion-Based Verification (ABV).
-
Maia EDA Launches New Automated Verification Tool (Thursday Dec. 10, 2009)
Maia EDA has today announced the availability of the Maia functional verification tool. Maia uses a description of the expected behavior of a device to automatically create a complete self-checking reactive testbench, so freeing engineers from the time-consuming, complex, and error-prone task of manual testbench creation.
-
Aldec Adds DO-254/ED-80 Library to HDL Design Rule Checker (Thursday Dec. 10, 2009)
Aldec announces today its latest Design Rule Checking application, ALINT™ 2009.10. The product includes “best-practice” design rules for fast design closure of safety critical DO-254/ED-80 Avionics designs.
-
Tensilica Delivers New Design Flow Support for Synopsys' Galaxy Implementation Platform Technologies (Tuesday Dec. 08, 2009)
Tensilica today announced that it now provides out-of-the-box automated design flow support for key technologies within Synopsys' Galaxy
-
Dolphin Integration promotes a design methodology ensuring High-Yield circuits despite Mismatch (Friday Dec. 04, 2009)
As the promoter of innovative Virtual Components of Silicon IP and methodologies for the Microelectronics Design Industry, Dolphin Integration takes the responsibility of setting up a method enabling the assessment of design yield for any memory generator.
-
Synfora Adds Support For Next Generation Xilinx Virtex-6 And Spartan-6 FPGA Devices To PICO Algorithmic Synthesis Tool (Tuesday Dec. 01, 2009)
Synfora announced a new version of its PICO Extreme™ FPGA C synthesis tool with support for the next-generation Xilinx Spartan-6 and Virtex-6 devices as well as seamless integration with the Xilinx Embedded Development Kit (EDK) tool suite.