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IP / SOC Products News

• MorethanIP and SOFTING AG announce cooperation for low cost complete system level solution for Industrial Ethernet with integrated switch (Wednesday Feb. 06, 2008)
  Softing AG and MorethanIP announce the integration of an 1588 Ethernet switch design from MorethanIP switch together with the Softing's realtime ethernet implementation utilizing low cost Altera FPGA’s.
  
  
• CEVA Expands its Multimedia Platform Offering with Addition of RealVideo and VC-1 Video Standards (Wednesday Feb. 06, 2008)
  The addition of these two popular video codecs further strengthens CEVA's MM2000 software-based architecture in the mobile multimedia market, adding to its supports of other leading video standards for mobile applications, including H.264, H.263, MPEG-4 and DivX.
  
  
• CAST Releases Improved IP Core for Controlling Large NAND-Flash SSD Memories (Tuesday Feb. 05, 2008)
  Representing the third generation of the company’s proven memory controller IP technology, the new NANDFLASH-CTRL core adds support for the newer high-capacity Multi-Level Cell (MLC) architecture while retaining support for traditional Single-Level Cell (SLC) memories.
  
  
• Wipro-NewLogic is the first company to provide Bluetooth 2.1 + EDR IP ready for qualification (Monday Feb. 04, 2008)
  Wipro-NewLogic, the semiconductor Intellectual Property (IP) business unit of Wipro Technologies today announced that its Bluetooth baseband IP (BOOST) Core has passed the official testing for Bluetooth 2.1 + EDR compliance in a Bluetooth Qualification Test Facility.
  
  
• Synopsys Expands Leading USB IP Portfolio With New IP for Link Power Management and High Speed Inter-Chip Standards (Monday Feb. 04, 2008)
  The new DesignWare USB LPM and HSIC digital controller and PHY IP reduce power consumption and area for USB-enabled chips.
  
  
• Faraday Offers the First Memory Compiler in UMC 65nm LL Process (Thursday Jan. 31, 2008)
  The 65nm LL memory solution features row redundancy, BIST test interface (BTI) and programmable sensing margin for manufacturing yield, and full-chip routability enhancement. Faraday's 65nm LL memory compiler is silicon-proven.
  
  
• Synopsys' DesignWare DDR Protocol Controller IP Integrated Into Arteris' Network-On-Chip Interconnect Solution (Wednesday Jan. 30, 2008)
  Arteris and Synopsys today announced the integration of Synopsys' DesignWare® DDR Protocol Controller IP and the Arteris NoC solution for complex system-on-chips (SoCs)
  
  
• Dolphin Integration launches a 32-bit processor, the densest core for SoC embedded Control Applications including Power Management (Tuesday Jan. 29, 2008)
  The FlipAPS32-051H is positioned as the smallest 32-bit core on the market but it is also dedicated to Ultra Low Power Consumption applications.
  
  
• Denali Announces NAND Flash Platform for PCI Express (Monday Jan. 28, 2008)
  The FlashPoint platform is a complete system design that provides a PCI Express (PCIe) interface to high-performance NAND Flash memory.
  
  
• Imagination Technologies First to Announce Conformant OpenVG 1.0.1 Implementation (Monday Jan. 28, 2008)
  Imagination Technologies reports that its POWERVR graphics acceleration technology is the world's first to pass the Khronos™ conformance tests for OpenVG™ 1.0.1.
  
  
• Mentor Graphics Releases Updated Serial ATA Host and Device Controllers for Storage Applications (Friday Jan. 25, 2008)
  Mentor Graphics Corporation (Nasdaq: MENT) today announced immediate availability of updated Serial ATA (SATA) Host/Device Intellectual Property (IP) controllers with added support for the most commonly used features in the latest SATA specification, Revision 2.6.
  
  
• ASIC Architect Announces the Availability of PCI Express Gen 2 Controller Cores (Tuesday Jan. 22, 2008)
  ASIC Architect, Inc. today announced the availability of PCI Express Gen 2 Controller Cores - in multiple lane width configurations - x16, x8, x4, x1. The product is developed based on PCI Express Specification 2.0 and is backward compatible with PCI Express Specification 1.1
  
  
• Freescale unleashes entry-level ColdFire core for mass market (Monday Jan. 21, 2008)
  Freescale Semiconductor has expanded its ColdFire® licensing program by offering its 32-bit V1 ColdFire core to the embedded community through IPextreme. For as little as $10,000 (USD), customers can obtain a license for the V1 ColdFire core, giving them design flexibility using proven microcontroller (MCU) technology based on three decades of evolutionary development.
  
  
• Dolphin Integration launches an embedded Li-Ion Battery Charger (Thursday Jan. 10, 2008)
  A Battery Charger for Lithium-Ion batteries is now available among Dolphin Integration's products for embedded power management solutions.
  
  
• Kilopass Collaborates with MagnaChip to Deliver Embedded Non-Volatile Memory Technology (Tuesday Jan. 08, 2008)
  Kilopass has completed the development of XPM on MagnaChip's 0.18um process node and expects to complete the silicon qualification in 2008.
  
  
• Imagination Technologies Announces Addition of AVS Chinese Video Standard to World-Leading Multi-Standard Video Core Family (Tuesday Jan. 08, 2008)
  Imagination Technologies announces the new POWERVR™ VXD380 advanced video decoder with support for all major HD and SD video formats, including the new Chinese AVS standard. VXD380 is the latest member of the growing POWERVR VXD/VXE family of video decoders and encoders.
  
  
• XpandR - a Wireless Multimedia System-on-Chip Platform to Be Launched by DSP Group (Friday Jan. 04, 2008)
  XpandR is a wireless multimedia-enabled system-on-chip platform, which supports DECT and Wi-Fi, and enables HD voice, streaming and sharing of video and music, email, web browsing and more.
  
  
• VeriSilicon Introduces VZ.AudioHD: A Complete, Licensable Audio Solution for Exploding High Definition Market (Wednesday Jan. 02, 2008)
  VZ.AudioHD platform includes a wide assortment of optimized high end audio software modules, high performance ZSP800 DSP processor, and system software solutions platform. For applications such as Blu-Ray/HD-DVD players and broadcast HD TV, the result is a single processor and complete software solution that significantly lowers development time and risk while saving cost compared to other processor IP solutions in the market.
  
  
• Sidense Broadens OTP Offering with Additional Process Nodes at SMIC (Friday Dec. 21, 2007)
  Sidense today announced that its one-time programmable (OTP) technology is available on Semiconductor Manufacturing International Corporation’s (SMIC) 180nm and 90nm processes.
  
  
• Digital Blocks Announces the DB-I2C Controller IP Core with the availability of Master-Slave, Master, and Slave Versions for the AMBA 2.0 APB Interconnect (Thursday Dec. 20, 2007)
  The DB-I2C IP Core targets systems-on-chip (SoC) ASSP, ASIC, and FPGA designs containing ARM embedded processors and the AMBA 2.0 APB on-chip bus, as well as other processors that support the APB bus.
  
  
• Wipro-NewLogics WiLD 801.11a/b/g IP Reference Platform receives Wi-Fi Certification (Tuesday Dec. 18, 2007)
  Wipro-NewLogic is announcing that its WiLD IP VD4 reference platform has been Wi-Fi CERTIFIED for IEEE802.11a, IEEE802.11b, IEEE802.11g, WPA - Personal, WPA2 - Personal, WMM, IEEE 802.11d and IEEE 802.11h.
  
  
• Chips&Media Now Supports RealVideo HD in Hardware IP (Tuesday Dec. 18, 2007)
  Chips&Media today announced that they are the first company to develop video IP supporting hardware decoding of RealVideo media at HD resolutions up to and including 1080p
  
  
• ARC configures a design flow for system-on-chip (Thursday Dec. 13, 2007)
  Configurable cores and subsystems developer ARC International (St. Albans, England) has developed and is refining a systems development platform that it says will change the way mobile multimedia systems are being designed.
  
  
• Lattice Delivers Industry's Fastest QDR II/II+ Memory Controller Support (Wednesday Dec. 12, 2007)
  The LatticeSC™ and LatticeSCM™ FPGA families now support QDRII/II+ rates up to 750Mbps. The high-speed QDR II and QDR II+ memory controller IP (intellectual property) is implemented in Lattice’s unique and low power Masked Array for Cost Optimization (MACO™) structured ASIC technology.
  
  
• Arasan Chip Systems Completes UNH Interoperability Testing for 10/100 Ethernet Solutions Suite (Wednesday Dec. 12, 2007)
  The Arasan 10/100 Ethernet Solution provides all the components needed for development, from the IP core to the Verification IP, software drivers and the hardware development platform. The IP core includes RMM compliant synthesizable RTL for 10/100 Media Access Controller (MAC) Core with MII or optional RMII interface, easy-to-use test environment and synthesis scripts.
  
  
• Sun Accelerates Growth of UltraSPARC CMT Eco System; Releases OpenSPARC(TM) T2 Processor RTL to Open Source Community (Tuesday Dec. 11, 2007)
  Sun Microsystems Inc. today delivered on the commitment it made in August by providing the OpenSPARC(TM) T2 RTL (register transfer level) processor design to the free and open source community via the GPL license. The OpenSPARC T2 processor is based on the UltraSPARC(R) T2 processor, the world's fastest commodity processor with eight cores and eight threads per core running the Solaris(TM) 10 Operating System (OS).
  
  
• Chipidea Introduces Industry's First Class D Audio Driver IP for Portable Consumer Applications (Monday Dec. 10, 2007)
  Chipidea today introduced the industry's first Class D Audio Driver intellectual property (IP) specifically designed for system-on-chip (SoC) devices manufactured in process nodes down to 65nm.
  
  
• ARC readies energy saving cores (Thursday Dec. 06, 2007)
  ARC International is readying a range of cores, dubbed Energy PRO, that adds active power management capability to its line-up of IP cores. The cores come validated with Cadence Low Power Solution and Common Power Format (CPF) through a partnership between the ARC, Cadence and Virage.
  
  
• Palmchip announces AcurX-Lite SoC Platform for Wireless Mobility (Tuesday Dec. 04, 2007)
  AcurX-Lite readily interfaces with major CPUs and proven 3rd party IP cores for the Wireless Mobility market. The new AcurX-Lite, comes with CPU bridge, memory subsystem bridge, DMA controller bridge, power management, interrupt controller, watchdog,general-purpose timers, two UARTs, I2C, SPI master, and a real-time clock. It supports multiple CPU cores (ARM, MIPS, ARC, Tensilica), multiple memory subsystems, 3rd party (Mentor, Synopsys) PCI, USB, Ethernet, Wireless and Video IP on a single chip.
  
  
• Xilinx Delivers Complete Virtex-5 FPGA Based Solutions for SPI-4.2 and SFI-4.1 Interfaces (Tuesday Dec. 04, 2007)
  Xilinx today announced complete solutions for the Optical Internetworking Forum (OIF) System Packet Interface (SPI) 4.2 and SerDes Framer Interface (SFI) 4.1 standards, the industry's highest performance channelized packet interfaces.