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IP / SOC Products News

• Arasan and Test Evolution announce Industry's first C-PHY / D-PHY Combo Compliance Analyzer with Arasan's Total MIPI IP Solution (Wednesday May. 23, 2018)
  Arasan Chip Systems is proud to announce the immediate availability of Test Evolution IP110 series C-PHY / D-PHY Combo protocol analyzers built using Arasan’s Total MIPI IP Solutions including C-PHY / D-PHY Combo IP cores.
  
  
• Chipus grows its battery charger IP family (Wednesday May. 23, 2018)
  Chipus announces the tape-out of its 3rd generation of battery charger IP with several improvements when compared with previous versions.
  
  
• Dolphin Integration introduces new Dual Port memory compilers in TSMC 40 nm (Monday May. 21, 2018)
  Dolphin Integration, leader in innovative design solutions for the next generation of energy-efficient System-on-Chips, has announced the launch of its new Dual Port RAM compiler ”ERA” in TSMC 40 nm. This cost-effective RAM compiler creates memories maximizing battery life whilst reducing silicon area.
  
  
• Synopsys Introduces Industry's First ASIL D Ready Embedded Vision Processor IP for ADAS Applications and Self-Driving Vehicles (Thursday May. 17, 2018)
  Synopsys today announced its new automotive safety integrity level (ASIL) B, C, and D Ready DesignWare® EV6x Embedded Vision Processors with Safety Enhancement Package (SEP) to accelerate the development of automotive system-on-chips (SoCs).
  
  
• New VDC-M (VESA Display Compression-M) IP Cores Launched By Hardent (Wednesday May. 16, 2018)
  Hardent, a VESA® member and leading provider of video compression IP cores, has today announced the launch of VDC-M encoder and decoder IP cores supporting the new VESA Display Compression-M standard.
  
  
• NetSpeed Furthers Leadership in Industrial, Factory Automation and Safety-critical Flight Systems with IEC 61508 Certification (Tuesday May. 15, 2018)
  NetSpeed Systems, Inc. today announced that its interconnect IP portfolio is now certified for the IEC 61508 functional safety standard. SGS-TÜV Saar GmbH, an independent accredited assessor, certified the IP in accordance with IEC 61508 Safety Integrity Level 3 (SIL3), the highest level possible for an IP-only component.
  
  
• MagnaChip and YMC to Offer Cost Effective 0.13 micron Multiple-Time Programmable (MTP) IP Solutions (Monday May. 14, 2018)
  MagnaChip Semiconductor Corporation (MagnaChip Semiconductor) (NYSE: MX), a designer and manufacturer of analog and mixed-signal semiconductor products, announced today the availability of 0.13 micron Multiple-Time Programmable Intellectual Property (MTP-IP) memory cores targeted for mobile and industrial applications.
  
  
• Crossbar ReRAM Enabling AI at the Edge (Monday May. 14, 2018)
  Crossbar, the ReRAM technology leader, today announced its ReRAM technology for artificial intelligence (AI) is available for licensing.
  
  
• Chipus concludes important milestone in the development of analog IP in SilTerra I18L technology (Thursday May. 10, 2018)
  Chipus is announcing the tape out of its Ultra-Low-Power IoT Analog IPs, targeted for SilTerra’s IoT platform, as part of the strategic partnership to provide analog IP solutions for customers.
  
  
• Arasan Announces Industries First MIPI I3C Master IP Core compliant to the I3C HCI Specifications v1.0 (Wednesday May. 09, 2018)
  Arasan Chip Systems announces the immediate availability of its MIPI I3C Host Controller Interface (“I3C HCI”) Master IP core compliant to the just released MIPI I3C HCI Specification Ver 1.0. The new I3C HCI specification standardizes the interface to enable building of common software drivers to enable easy access to the I3C HCI v1.0 Compliant Host Controllers.
  
  
• IntelliProp Announces NVMe-to-SATA Bridge IP Core (Wednesday May. 09, 2018)
  IntelliProp, Inc., a leader in innovative Intellectual Property (IP) Cores and semiconductors for Data Storage and Memory applications, announced today the release of the IPP-NV186A-BR, NVMe-to-SATA Bridge IP Core.
  
  
• NetSpeed and Northwest Logic Partner to Boost Performance in Hyperscale and Automotive SoCs (Tuesday May. 08, 2018)
  NetSpeed Systems, Inc. and Northwest Logic today announced a partnership to deliver high throughput memory subsystem solutions for customers designing SoCs for hyperscale and automotive applications.
  
  
• Silex Inside upgrades IP offering for compatibility with Chinese security standards (Tuesday May. 08, 2018)
  Silex Inside, the leading provider of IP cores for cryptography, announces that it has upgraded its hardware IP blocks for security to adhere to the SM2, SM3, and SM4 standards for secure communication defined by the Chinese authorities.
  
  
• Comcores Announce Availability of flexible eCPRI IP solution (Tuesday May. 08, 2018)
  Denmark Headquartered Comcores ApS, a fast growing specialized supplier of silicon intellectual property (SIP) today announced the availability of eCPRI 1.0 IP targeting FPGA and ASIC devices.
  
  
• Chips&Media Unveils its first Computer Vision IP (Monday May. 07, 2018)
  Chips&Media Inc., a leading global video IP provider, announced the launch of its first Computer Vision IP, detecting objects with a capability to process 4K resolution at 60 frames per second input in real-time.
  
  
• StreamDSP Announces Availability of VITA 17.3 sFPDP Gen 3 IP Core (Monday May. 07, 2018)
  StreamDSP announces immediate availability of VITA 17.3 sFPDP Gen 3 IP Core. The recently approved VITA 17.3 specification, also known as Serial Front Panel Data Port (sFPDP) Gen 3, is a next-generation communications protocol designed as the successor to VITA 17.1.
  
  
• New Arm IP Helps Protect IoT Devices from Increasingly Prevalent Physical Threats (Wednesday May. 02, 2018)
  To protect the IoT, we need to think beyond software attacks and physical security requires our attention more than ever. As new use cases emerge, this protection won’t just be required for payment and identity applications, it will need to be integrated for use cases such as smart lighting, connected door locks, smart meters or automotive applications.
  
  
• Arm Physical IP to Accelerate Mainstream Mobile and IoT SoC Designs on TSMC 22nm ULP/ULL Platform (Wednesday May. 02, 2018)
  Arm announced today its Arm® Artisan® physical IP will be used in TSMC’s 22nm ultra-low power (ULP) and ultra-low leakage (ULL) platform for Arm-based SoCs. TSMC 22nm ULP/ULL is optimized for mainstream mobile and IoT devices, enabling improved performance for Arm-based SoCs, and reductions in both power and area when compared to the previous-generation TSMC 28nm HPC+ platform.
  
  
• New MIPS I7200 Processor Core Delivers Unmatched Performance and Efficiency For Advanced LTE/5G Communications And Networking IC Designs (Tuesday May. 01, 2018)
  MIPS, provider of the widely used MIPS processor architecture and IP cores for licensing, today announced the I7200 multi-threaded multi-core processor, a new high performance licensable IP core in their midrange 32-bit product lineup.
  
  
• Cadence Prototypes First IP Interface in Silicon for Preliminary Version of DDR5 Standard Being Developed in JEDEC (Tuesday May. 01, 2018)
  The Cadence test chip was fabricated in TSMC’s 7nm process and achieves a 4400 megatransfers per second (MT/sec) data rate, which is 37.5 percent faster than the fastest commercial DDR4 memory at 3200MT/sec.
  
  
• Synopsys and TSMC Collaborate to Deliver DesignWare Foundation IP for Ultra-Low Power TSMC 22-nm Processes (Monday Apr. 30, 2018)
  Synopsys today announced its collaboration with TSMC to develop DesignWare® Foundation IP for TSMC's 22-nanometer (nm) ultra-low power (ULP) and ultra-low leakage (ULL) processes. DesignWare Foundation IP, including logic libraries, embedded memories, and one-time programmable (OTP) non-volatile memories (NVM) on TSMC's 22-nm processes, enables designers to significantly reduce power consumption while meeting performance requirements for a wide range of applications.
  
  
• PLDA Announces XpressCCIX Controller IP Supporting The Cache Coherent Interface For Accelerators (CCIX) Standard (Monday Apr. 30, 2018)
  PLDA today released its XpressCCIX IP, supporting CCIX™ or Cache Coherent Interconnect for Accelerators (X). The decision to support CCIX is fueled by an increasing demand for higher throughput for PCIe-based systems, driven largely by enterprise and data center customers.
  
  
• SST and UMC Announce Qualification of Embedded SuperFlash Technology on 40 nm CMOS Process (Monday Apr. 30, 2018)
  Microchip Technology subsidiary Silicon Storage Technology (SST), and United Microelectronics Corporation announced the full qualification and availability of SST’s embedded SuperFlash non-volatile memory on UMC’s 40 nm CMOS platform. The 40 nm process features a more than 20 percent reduction in embedded Flash cell size and a 20-to-30 percent reduction in macro area over their 55 nm process.
  
  
• eMemory introduces more security features to its eNVM IP for TSMC 7nm Process (Friday Apr. 27, 2018)
  eMemory today announced the successful verification of its secure eNVM IP for TSMC’s advanced processes, and the company is introducing more security features to the eNVM solution for TSMC’s 7nm process technology in the coming months.
  
  
• M31 Technology Deploys the Full Range of IP for TSMC 22nm ULP/ULL Process (Wednesday Apr. 25, 2018)
  M31 Technology Corporation (Taiwan stock code: 6643), a global Silicon Intellectual Property (IP) boutique, today announced its collaboration with TSMC to deploy the full range of IP for TSMC 22nm ULP/ULL technology.
  
  
• T2M announces availability of Bluetooth SIG qualified v5 Bluetooth Low Energy Controller, Stack and Profiles IP from Mindtree (Thursday Apr. 19, 2018)
  T2M announced the availability of Mindtree’s BQB (Bluetooth Qualification Body) qualified Bluetooth v5 Controller, Stack and Profiles (Declaration ID #D038059 and #D038060). This makes Mindtree the first company to qualify a full featured Bluetooth Low Energy 5 IP with TCRL 2 Specifications.
  
  
• Rambus Launches CryptoManager RISC-V Root of Trust Programmable Secure Processing Core (Monday Apr. 16, 2018)
  Rambus Inc. (NASDAQ: RMBS) today announced the availability of the CryptoManager Root of Trust, a fully programmable hardware security core built with a custom RISC-V CPU.
  
  
• DapTechnology Releases 1394/AS5643 IP for Microsemi IGLOO2 and SmartFusion2 FPGA Devices (Thursday Apr. 12, 2018)
  DapTechnology B.V. today announced the immediate availability of FireCore General Purpose Link (GPLink) for the Microsemi (now Microchip) IGLOO2 and SmartFusion2 FPGA devices.
  
  
• Cadence Boosts Vision and AI Performance with New Tensilica Vision Q6 DSP IP (Wednesday Apr. 11, 2018)
  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Cadence® Tensilica® Vision Q6 DSP, its latest DSP for embedded vision and AI built on a new, faster processor architecture. The fifth-generation Vision Q6 DSP offers 1.5X greater vision and AI performance than its predecessor, the Vision P6 DSP, and 1.25X better power efficiency at the Vision P6 DSP’s peak performance.
  
  
• Aldec's HES UltraScale+ Reconfigurable Accelerator and Northwest Logic's PCI Express Cores Provide Proven PCI Express Solution (Wednesday Apr. 11, 2018)
  Aldec, has used Aldec’s HES-XCVU9P-QDR UltraScale+ board with Northwest Logic’s Expresso 3.0 core for PCI Express® and AXI DMA Back-End Core to demonstrate a proven PCI Express solution which provides over 6 GB/s PCI Express throughput.