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IP / SOC Products News

• Digital Blocks I2C & SPI Controller IP Core Families Extend Lead in Sensor Interface to Host Processors with System-Level Features & Low Power (Wednesday Sep. 30, 2015)
  Digital Blocks extends its leadership in I2C and SPI Controller Verilog IP Cores targeting IC Sensor interfaces to Host Processors.
  
  
• Imagination's Ensigma communications IP receives Wi-Fi CERTIFIED ac certification and Bluetooth Smart qualification (Tuesday Sep. 29, 2015)
  Imagination Technologies (IMG.L) announces it has received certification for Wi-Fi CERTIFIED™ ac and qualification for Bluetooth® Smart for its high-performance Ensigma Explorer radio processing unit (RPU) communications IP.
  
  
• Open-Silicon Announces Comprehensive High Bandwidth Memory (HBM) Gen2 IP Subsystem Solution (Tuesday Sep. 29, 2015)
  Open-Silicon, a system optimized ASIC solution provider, announced today the industry's first High Bandwidth Memory (HBM) subsystem IP. The solution is available for 2.5D ASIC design, starts today and will also be made available as licensable Intellectual Property (IP).
  
  
• Synopsys Announces Industry's First Security IP Solutions for New SHA-3 Cryptographic Hash Standard (Tuesday Sep. 29, 2015)
  Synopsys has announced the industry's first security IP solutions compliant to the Secure Hash Algorithm-3 (SHA-3) cryptographic standard from the National Institute of Standards and Technology (NIST).
  
  
• Shikino Launches Still Image Codec IP Obtaining 16X Faster Image Processing (Monday Sep. 28, 2015)
  Shikino today announced that it has launched a new still image codec IP, “KJN-8EX”, and commenced sales on July 31, 2015. As a new product from the “KJN series” with the world’s top share in the still image compression/decompression technology, Shikino developed this still image codec IP which has the high-speed image processing performance, 16X speed (16 data/clock), in the JPEG compression/decompression with high bit depths (8-bit/10-bit/12-bit).
  
  
• Synopsys Accelerates Development of IoT Designs with Industry's Most Comprehensive IP Portfolio (Tuesday Sep. 22, 2015)
  Synopsys today announced a comprehensive portfolio of IP optimized to address the security, wireless connectivity, energy-efficient and sensor processing requirements for a wide range of Internet of Things (IoT) applications such as wearables, smart appliances, metering and wireless sensor networks.
  
  
• New performances specified by Dolphin Integration for minimizing Power Regulator Capacitances (Monday Sep. 21, 2015)
  Reducing the cost of Bill-of-Material (BoM) remains SoC Integrators' vital challenge for IoT applications, while minimizing power consumption demands the acute complexity of mode control for Dynamic Voltage and Frequency "Stepping" (DVFS).
  
  
• Arasan Announces Automotive Grade MIPI DPHY IP For 40nm (Monday Sep. 21, 2015)
  Arasan Chip Systems today announced the availability of it’s MIPI DPHY IP Core qualified for use in extreme automobile operating conditions using the 40nm process nodes from Global Foundries and additional silicon foundry providers.
  
  
• Synopsys Successfully Tapes Out Broad IP Portfolio for TSMC 10-nm FinFET Process (Thursday Sep. 17, 2015)
  Synopsys today announced the successful tape-out of a broad portfolio of DesignWare® Interface and Foundation IP on TSMC's 10-nanometer (nm) FinFET process, reducing risk for designers who want to take advantage of the power, area and performance improvements offered by the process.
  
  
• D32PRO, fully scalable & royalty-free 32-bit CPU from DCD (Thursday Sep. 17, 2015)
  Digital Core Design, an IP Core provider and a System-on-Chip design house from Poland, has introduced the newest CPU. The D32PRO is a 32-bit, deeply embedded and royalty-free IP Core. This silicon proven solution, based on RISC architecture but mastered on DCD’s experience dated since 1999, boosts performance to 1.48 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz.
  
  
• Flex Logix Extends Embedded FPGA-in-SoC Architecture with New Block RAM and DSP Cores (Thursday Sep. 17, 2015)
  Flex Logix today announced the extension of its core FPGA logic architecture to include Block RAM (BRAM) and DSP cores. Both BRAM and DSP are popular extensions found in traditional stand-alone FPGA products. The addition of low-latency memory and signal processing capabilities significantly increases the range of applications addressed by Flex Logix’ EFLX™ embedded FPGA-in-SoC architecture.
  
  
• Cadence Announces Broad IP Portfolio for TSMC 10nm FinFET Process (Wednesday Sep. 16, 2015)
  Cadence today announced a broad intellectual property (IP) portfolio for TSMC’s 10nm FinFET (N10) process. Cadence has already secured multiple design wins with this portfolio and is actively engaged with customers as adoption of TSMC’s leading-edge process grows.
  
  
• RFEL announces new version of award-winning ChannelCore Flex advanced Channeliser IP core (Tuesday Sep. 15, 2015)
  
  
  
• eMemory Announces the First Verified NeoFuse OTP IP in 16nm FinFET Plus Process (Tuesday Sep. 15, 2015)
  eMemory announces its new technology breakthrough–the availability of its One-Time Programmable (OTP) NeoFuse technology in mainstream 16nm FinFET Plus process, as well as the development and verification of high-capacity (256k bit) and low-voltage (<0.8V) silicon IPs. It is the world’s first OTP technology verified in 16nm FinFET Plus process.
  
  
• SilabTech announces the release of its USB 3.1 Gen 2 Compliant 10 Gbps SERDES IP Core (Monday Sep. 14, 2015)
  SilabTech, leading supplier of High Speed Interface intellectual property designs (IPs), announced today the release of its USB 3.1 Gen 2 SERDES IP Core. SilabTech has already delivered the 1st generation of USB 3.0 SERDES, also known as USB SuperSpeed Gen 1 ( 5 Gbps) to customers and now announced the 2nd Generation, USB 3.1 SuperSpeed Gen 2 with Data Transfer Speed of 10 Gbps.
  
  
• intoPIX to Showcase New TICO Compression Performances on FPGAs and CPU for UHD/4K and HFR (Monday Sep. 14, 2015)
  intoPIX, leading provider of video compression solutions, today announced that its TICO lightweight video compression technology has extended its performance on FPGA and CPU platforms.
  
  
• New DesignWare ARC EM Processors Deliver Up to 3X Higher DSP Performance (Thursday Sep. 10, 2015)
  Synopsys today announced availability of the DesignWare® ARC® EM9D and EM11D Processors. The EM9D and EM11D cores implement an enhanced version of the ARCv2DSP instruction set architecture (ISA), combining RISC and DSP processing with support for an XY memory system to boost digital signal processing performance while minimizing power consumption.
  
  
• RFEL announces updates to its flagship "Video Fusion" high definition video processing IP core (Thursday Sep. 10, 2015)
  RFEL has announced updates to its flagship Video Fusion™ high definition, video processing IP core for FPGA and System-on-Chip systems, that now has sophisticated enhancement and customisable pseudo-colour mapping features to help product designers add a competitive edge to their systems and to aid the user overcome the challenges of Degraded Visual Environments (DVEs).
  
  
• Barco Silex releases new patent-free and lightweight VC-2 LD video codec at IBC 2015 (Wednesday Sep. 09, 2015)
  At IBC 2015 Show in Amsterdam, Barco Silex, the leading provider of video compression IP cores for ASIC and FPGA, announced that the new VC-2 Low Delay codec is now available for licensing to broadcast equipment manufacturers.
  
  
• Menta Delivers Off-the-Shelf Embedded FPGA IP Cores that Enable a New Level of Flexibility to be built into Complex SOCs (Wednesday Sep. 09, 2015)
  Menta SAS today announced a family of pre-defined off-the-shelf IP cores that enable a new level of flexibility to be built into next-generation complex System on Chip (SOC) devices.
  
  
• With Ultimate Craftsmanship, M31 Develops IP Solutions for IoT (Wednesday Sep. 09, 2015)
  M31 Technology, a global boutique silicon intellectual property (IP) developer announced various ultra low power IPs to target the Internet of things (IoT) related design projects.
  
  
• Arasan Chip Systems Announces Availability of ONFI 4.0 Compliant NAND Flash Controller IP & PHY Solution (Thursday Sep. 03, 2015)
  NAND flash memory applications are ever evolving, placing demands on the designers to continuously push the envelope on performance and power consumption. Arasan addresses these challenges by offering its Arasan ONFI 4.0 Compliant NAND Flash Controller IP solution that provides a performance boost by increasing data transfer rates to 800 MT/s – or 800MB/s for an 8 bit interface – and reduces power consumption by more than 50%.
  
  
• Synopsys Announces Availability of Logic Library and Embedded Memory IP for Mie Fujitsu Semiconductor 40-nm Low-Power Process (Tuesday Sep. 01, 2015)
  Synopsys, Inc. (Nasdaq:SNPS) today announced the availability of DesignWare® Logic Library and Embedded Memory IP for the Mie Fujitsu Semiconductor 40-nanometer low-power (40LP) process.
  
  
• Open-Silicon and Cadence Collaborate on DSP-Based Custom SoC Platform (Thursday Aug. 27, 2015)
  Open-Silicon, a system optimized ASIC solution provider, announced today the collaborative development of a scalable SoC subsystem using the Cadence® Tensilica® Fusion digital signal processor (DSP).
  
  
• Build an ultra low power SoC thanks to implementation-ready solutions from Dolphin Integration (Monday Aug. 24, 2015)
  Relying on 30 years of experience in SoC design, Dolphin Integration has developed all the IP contributors for an ultra-low-power SoC, in partnership with TSMC, particularly relevant for IoT applications.
  
  
• CEVA Announces the Certification of RivieraWaves Bluetooth Smart 4.2 Platform IP (Tuesday Aug. 18, 2015)
  CEVA today announced that its RivieraWaves Bluetooth Smart 4.2 IP platform has been fully certified by the Bluetooth Special Interest Group (SIG).
  
  
• IP-Maker to introduce PCIe Gen3 capable NVMe controller IP (Wednesday Aug. 12, 2015)
  IP-Maker introduces its new version of NVMe controller IP. PCIe Gen3 capable, this full hardware architecture UNH-IOL compliant, will reduce dramatically the latency of NVMe storage systems.
  
  
• Chips&Media announces new small size multi-standard video codec IP targeting for Low end AP (Tuesday Aug. 11, 2015)
  Chips&Media, Inc. announced today the availability of CODA7Q - ultra small size new multi-standard video codec IP targeting for low end AP market. CODA7Q is an updated version of CODA7L supporting HEVC (H.265) Decoder IP in a single core
  
  
• Dolphin Integration and TSMC collaborate on Low-Power IoT Subsystem Design (Monday Aug. 10, 2015)
  Dolphin Integration today announced a collaborative effort with TSMC to ease the design and optimization of Internet of Things (IoT) subsystems for System-on-Chip (SoC) integrators.
  
  
• Xilinx Announces LDPC Error Correction IP Fundamental to Enabling Next Generation Flash-Based Applications for the Cloud and Data Center Storage Market (Monday Aug. 10, 2015)
  Xilinx today announced its Low-Density Parity-Check (LDPC) error correction IP fundamental to enabling next generation Flash-based applications for the cloud and data center storage market.