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FPGA / CPLD Articles

• Partial reconfiguration in FPGA rapid prototyping tools (Sep. 22, 2011)
  FPGA rapid prototyping tools are greatly useful at the time of designing and testing complex signal processing systems, due to their graphic programming environment and the possibility they offer to functionally simulate the whole system before synthesizing the code. Furthermore, FPGA partial reconfiguration is a very effective feature when trying to reduce the resources needed to implement systems dealing with multiple functionalities. Unfortunately, this characteristic is not supported by the rapid prototyping tools. This paper exhibits the state of the art of partial reconfiguration in FPGAs and rapid prototyping tools and shows the way of linking them in a single design.
  
  
• How to achieve 1 trillion floating-point operations-per-second in an FPGA (Sep. 15, 2010)
  Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This article describes how floating-point technology in FPGAs is not only practical today, but that the processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible and can be implemented on a single FPGA die.What’s changed?
  
  
• Using switched capacitors to create programmable analog logic blocks in mixed-signal designs (Aug. 18, 2010)
  Any physical system design needs both analog and digital functionality. Achieving a modular, programmable design is crucial for the demanding applications of future, which has led to more and more designs integrating subsystems and using mixed-signal architectures.
  
  
• Repeatable results with design preservation (Jun. 10, 2010)
  Increasingly, FPGA designs are no longer just the 'glue logic' of the past; they are becoming more complex every year, often incorporating challenging such as PCI Express cores. Time spent trying to maintain timing in these modules is not only frustrating, but often unproductive as well. The design preservation flow solves this issue by allowing the customer to meet timing on the critical module(s) of the design and then reuse the implementation results in future iterations.
  
  
• Protecting FPGAs from power analysis security vulnerabilities (May. 20, 2010)
  This article introduces static power analysis and dynamic power analysis attacks, discusses how these vulnerabilities apply to FPGAs, and provides guidance about the types of countermeasures that can be implemented to protect FPGAs against these attacks.
  
  
• The Need for Variable Precision DSP Architecture (May. 06, 2010)
  FPGAs with variable-precision DSP block architecture are the only programmable devices that can efficiently support many different precision levels including floating-point implementations. This DSP architecture enables the next-generation of high-precision and high-performance signal processing applications.
  
  
• Timing Closure on FPGAs (Apr. 22, 2010)
  While designers place great emphasis on coding and simulation, they often have only a nodding acquaintance with the internal workings of the silicon within an FPGA. As a result, incorrect logic synthesis and timing problems, rather than logic errors, are the cause of most logic failures.
  
  
• Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1) (Mar. 18, 2010)
  This is a two-part article that focuses on the design guidelines and describes how to implement DDR or DDR2 external memory interfaces (EMIFs) using FPGAs via ALTDLL and ALTDQ_DQS megafunctions.
  
  
• Viewpoint: Your future is programmable (Mar. 11, 2010)
  The state of the electronics industry today, and certainly in the future, directly challenges that traditional view of technology-focused product design evolution.
  
  
• Arrgghh! My FPGA's not working: Problems with the RTL (Feb. 03, 2010)
  We all tend to have high levels of faith in various aspects of the FPGA design flow, but it's not long before we discover how unfounded this faith can be. In reality, bugs can manifest themselves in any portion of the FPGA design flow.
  
  
• Increasing bandwidth in industrial applications with FPGA co-processors (Feb. 02, 2010)
  This article discusses the general issues of moving part, or all, of a DSP industrial application onto an FPGA using system software design tools. Using an FPGA and automated design software, design engineers have the ability to optimize system performance in ways not possible with a traditional DSP.
  
  
• Using an FPGA to tame the power beast in consumer handheld MPUs (Jan. 18, 2010)
  Shorter product lifecyles and lower volume consumer product families have led designers increasingly to turn to the FPGA for handheld-product development. But doing so requires grappling with new challenges in terms of area, speed and power.
  
  
• Power Supply Design Considerations for Modern FPGAs (Jan. 11, 2010)
  Today's FPGAs tend to operate at lower voltages and higher currents than their predecessors. Consequently, power supply requirements may be more demanding, requiring special attention to features deemed less important in past generations. Failure to consider the output voltage, sequencing, power on, and soft-start requirements, can result in unreliable power up or potential damage to the FPGA.
  
  
• Accelerating Bioinformatics Searching and Dot Plotting Using a Scalable FPGA Cluster (Nov. 30, 2009)
  This paper presents an FPGA-based accelerated solution for DNA sequencing and dot plotting. It describes how multiple FPGA devices can be deployed to create a scalable cluster dedicated to the task of analyzing large amounts of data, and how this clustered hardware application can be connected to a software application for visualization and analysis.
  
  
• High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems (Nov. 19, 2009)
  Many video systems are implemented with feature-rich FPGA and multi-rate SDI integrated circuits that support high performance professional video transport over long distances. But FPGAs demand high density routing with fine trace width while high-speed analog SDI routing demands impedance matching and signal fidelity. This paper outlines the layout challenges facing hardware engineers and provides recommendations for dealing with these challenges.
  
  
• Enable low power design with FPGAs (Nov. 05, 2009)
  Size and power considerations are now often the top priority in many system designs, but portability and long-lasting power can become conflicting design requirements. FPGAs seem like the best choice but warning: not all FPGAs are created equal, especially in portable, low-power applications.
  
  
• Clock sources with integrated power supply noise rejection simplify power supply design in FPGA-based systems (Oct. 08, 2009)
  By their nature, FPGAs are power hungry devices with complex power delivery requirements and multiple voltage rails. A single chip commonly consumes multiple watts of power while operating from 1.8 V, 2.5 V and 3.3 V rails. Activating high speed on-chip SERDES can increase power consumption by several watts and complicate the power delivery strategy.
  
  
• Don't Let Metastability Cause Problems in Your FPGA-Based Design (Oct. 01, 2009)
  This article describes metastability in FPGAs, explains why the phenomenon occurs, and discusses how it can cause design failures. It also explains how mean time between failures (MTBF) is calculated from design and device parameters, and presents techniques to improve system reliability with increased MTBF.
  
  
• Enabling Secure Integration of Multiple IP Cores in the Same FPGA (Sep. 28, 2009)
  In this work, we discuss a security mechanism for integrating multiple IP cores into the same FPGA-bound design, maintaining their individual security, and preventing their theft and/or over deployment. The system utilizes robust cryptographic techniques and device-specific IP descriptions to achieve the desired goals.
  
  
• Building high-speed FPGA memory interfaces (Sep. 03, 2009)
  This article examines the architecture behind the I/O blocks in high-end FPGAs and how these FPGAs are able to achieve 533 MHz or 1067 Mbps data rates. It also examines the tools that are used to build a memory interface, and provide a brief overview of the timing budget.
  
  
• Xilinx Virtex-6 FPGA User Guide Lite (Aug. 06, 2009)
  This paper gives potential users an easy-to-grasp idea of the device functions of Xilinx Virtex-6 FPGAs. It describes the functionality of these devices in far more detail than in the data sheet—but avoids the minute implementation details covered in the various Virtex-6 FPGA user guides.
  
  
• Deinterlacing with FPGA for HDTVs (Jul. 16, 2009)
  This article explores the different deinterlacing techniques and examines how FPGAs are increasingly being used for any sufficiently complex deinterlacing function. The article also examines the hardware tradeoffs when implementing different deinterlacing algorithms.
  
  
• Rapid debug of serial buses in FPGAs (Jul. 01, 2009)
  Low-speed serial buses remain prevalent across several electronics industries. Serial buses such as I2C, SPI, CAN, LIN, and RS-232 are often key points for debugging designs with FPGAs which higher speed serial buses quickly pass data from chip to chip. Historically, capturing and decoding the information required significant manual effort if using an oscilloscope or the purchase of custom tools. Oscilloscope vendors now incorporate significant application technology that simplifies debug of low-speed serial buses.
  
  
• Programmability in portable design: the five modes of motivation (Jun. 04, 2009)
  Wendy Lockhart explains that flash based FPGAs can replace ASICs in portable devices.
  
  
• Altera Stratix IV User Guide Lite (Jun. 01, 2009)
  This paper provides potential users an easily read and easy-to-understand overview of the capabilities of the device functions of Altera's Stratix IV FPGAs. It succinctly describes the feature set, the architecture innovations, and the process techniques that when combined make the Stratix IV FPGA the industry leader in both power and performance. Further, the article describes the functionality of these devices in far more detail than in the data sheet, but avoids the minute implementation details covered in the Stratix IV FPGA Device Handbook.
  
  
• How to reduce power consumption in CPLD designs with power supply cycling (Mar. 12, 2009)
  Power supply cycling offers designers a viable means to achieve the desired features as well as low power consumption in their CPLD designs.
  
  
• How to detect solder joint faults in operating FPGAs in real time (Mar. 05, 2009)
  Without early detection, electrical anomalies caused by solder joint faults can result in the catastrophic failure of mission-critical equipment.
  
  
• PRODUCT HOW-TO: Bringing programmability to portable design (Feb. 27, 2009)
  How Actel's flash based FPGAs can be used to replace ASICs and SRAM-based FPGAs in many portable devices
  
  
• How to control analog output from a CPLD using a pulse width modulator (Feb. 26, 2009)
  This article shows how a CPLD can replace a digital-to-analog converter, allowing it to drive an audio speaker or control things like LED intensity, motor speed, and servo position.
  
  
• Power-aware FPGA design (Part 3) (Feb. 19, 2009)
  This three-part article covers several aspects of FPGA power consumption; it also provides a new look at power dissipation numbers, and questions the traditional methods of estimating and measuring power.