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IP / SOC Products Articles

• Advancing Network Packet Management for Converged NIC (Feb. 09, 2012)
  In a Data center, with the advent of Virtualization and Virtual Ethernet Bridging, the server to network edge is becoming an increasingly important area of the infrastructure. The most common types of networks used in enterprise Data Centers are Ethernet for LAN and FC for SAN and are converging. Fiber Channel (FC) is a lightweight, high performance protocol usually with in a SAN (limited area), where as iSCSI running over traditional TCP/IP protocols (routable) and existing Ethernet Infrastructure. These have different topologies, administrators, security, and performance requirements.
  
  
• Optimizing System Management in the Platform SoC Era (Jan. 26, 2012)
  Consumer focused SoCs have evolved into platform architectures that are now being driven by requirements from operating systems such as Android, iPhone. Linux, and Windows and the thousands of applications they support. Overtime more of the system is moving into silicon . As a result, system management functions have moved into the SoC. Traditional feature based regression testing at the silicon level must now be increasingly complimented with complex system level testing in order to maintain a high level of system coverage across SoC road maps.
  
  
• icyflex: an ultra-low power DSP core for portable applications (Nov. 14, 2011)
  The icyflex family of ultra low power 16/32-bit RISC processor cores developed by CSEM offers a flexible architecture that allows for different com-binations of control and DSP functionality. These processors target applications requiring long battery life at the same time as on-chip processing power. Three silicon-proven icyflex cores are available, consuming as little as 6 μW/MHz.
  
  
• Embedded antifuse NVM: A mission critical IP for display driver ICs (May. 02, 2011)
  This Product How-To article discusses use of antifuse nonvolatile memory in display driver ICs (DDI) and touch sensor controllers and how proprietary technology from Kilopass can be used to make NVM an integral part of a system-on-chip design.
  
  
• Systematic approach to verification of a mixed signal IP - HSIC PHY case study (Apr. 21, 2011)
  This paper discusses verification process of a mixed signal core of an HSIC PHY. After explaining the specific topic related with HSIC comparison to USB, the verification strategy is shown. The strategy is explained from the top level point of view, and detailed description is covered in subsequent sections. In following sections the system level testbench and interoperability testbenches are explained parallel to local testbenches for analog block characterization.
  
  
• Cache Evaluation Software: A Dynamically Configurable Cache Simulator (Apr. 18, 2011)
  The memory hierarchy (including caches and main memory) can consume as much as 50% of an embedded system power. This power is very application dependent, and tuning caches for a given application is a good way to reduce power consumption. However application programs are complex and include many subroutines, each of them having their own optimal cache configuration. We developed a low power dynamically reconfigurable cache controller and its simulator called Cache Evaluation Software.
  
  
• M-PHY benefits and challenges (Apr. 13, 2011)
  The M-PHY supports plesiochronous as well as mesochronous operations, speeds from 10Kbps up to data rates of 6Gbps while maintaining low power operation, achieving low electro-magnetic-interference (EMI), supporting a variable number of links, sub-links, and data lanes, multiple media options, and a growing number of use-case in traditional and non-traditional mobile applications.
  
  
• Minimal Effort Chip Design Using IP (Apr. 11, 2011)
  In order to speed up design cycles and to reduce development costs, use of external IP is increasingly becoming more popular. However, this IP based design is not free of considerable effort and saves only about half of the effort required to develop the IP internally. The concept of Intelligent Design Automation (IDA) is presented here which uses intelligent algorithms such as matchmaking algorithm, rating systems, fuzzy logic, and multi-criteria optimization. This paper also presents the idea of IP Integration Automation,or I2A, tools.
  
  
• The Power and Bandwidth Advantage of an H.264 IP Core with 8-16:1 Compressed Reference Frame Store (Apr. 04, 2011)
  Power is an increasingly important consideration for the majority of system designers. This is particularly true in the case of small handheld consumer devices such as cameras, camcorders and mobile phones. In such devices, video compression technology is used that relies on power hungry DRAMs to store the reference frames during the encoding and decoding process.
  
  
• Complete NAND Flash Solution: Logic, PHY and File System Software (Mar. 28, 2011)
  NAND FLASH memories are non-volatile, inexpensive and of high capacity. These characteristics make these devices ideal for fulfilling the storage requirements in the exploding mobile device market.
  
  
• Analog IP for multimedia SoCs: an eye on a world of essential analog features (Mar. 23, 2011)
  This article unveils how the analog functions that are built into an analog IP multimedia subsystem should be carefully selected to address the particular application requirements while guaranteeing the smallest silicon area and the lowest power consumption, a two-fold challenge that is commonly faced today by both system-on-chip (SoC) integrators and IP providers.
  
  
• Analog switches in D-PHY MIPI dual camera/dual display applications (Part 2 of 2) (Mar. 17, 2011)
  When inserting an analog switch, the key influencing factor is still the incident wave response, as the switch can be seen as a discontinuity. The switch RC characteristics have to be optimized to facilitate good “eye” performance by minimizing reflections and edge rate degradation.
  
  
• A 55-nm Ultra Low Leakage SRAM Compiler with Optimized Power Gating Design (Mar. 14, 2011)
  In this paper an optimized power gating design on a 55-nm Static Random Access Memory (SRAM) compiler is presented. Two low leakage modes: retention and sleep mode are discussed. The arrangement of power gating (P.G.) MOS is especially considered for the compiler design. The proposed method achieves an obvious advantage in leakage control of low leakage mode for memory compiler. Simulation data shows a 4× leakage reduction for retention mode, and a 50× leakage reduction for sleep mode for a 512k density instance compared to original design.
  
  
• Analog switches in D-PHY MIPI dual camera/dual display applications (Part 1 of 2) (Mar. 14, 2011)
  This article describes how, with the use of analog switches, the legacy processors can easily interface with dual cameras or dual displays without impacting the current system architecture and can, in actuality, enhance system performance by isolating the transmission line effects of the second camera (or display) loading the MIPI bus.
  
  
• Using PCI Express as a fabric for interconnect clustering (Mar. 08, 2011)
  A number of interconnect technologies are vying to replace GbE, with the top contenders being 10 Gigabit Ethernet (10GbE), InfiniBand (IB) and PCI Express (PCIe). The latter, with its advanced capabilities, makes a strong case for becoming the ideal backplane interconnect solution.
  
  
• CPUs in FPGAs: many faces to a trend (Mar. 07, 2011)
  Whether as synthesizable soft cores or hard cores on the die, CPUs are showing up in more FPGA designs, bringing with them important challenges for designers.
  
  
• Adding encryption to disk drives is made easy using an IP core (Mar. 03, 2011)
  The availability of low-cost IP cores that implement AES-128 or AES-256 opens up the possibility that all drives can have high-grade encryption as standard.
  
  
• MIPI™ MPHY - An introduction (Feb. 28, 2011)
  Recognizing the need for high bandwidth pipes, the MIPI alliance has been defining standards for these serial interfaces. D-PHY, which was ratified 1.5 years ago but with a near final version for 3 years, supports 1Gbps per lane. The M-PHY specification, whose 1.0 version is about to be ratified, supports about 1.25Gbps/1.5Gbps and has options to support 2.5Gbps/3Gbps and 5Gbps/6Gbps per lane.
  
  
• Virtual Channels Hardware Support in Switches in Relation to NoC Costs, Functions and Features (Feb. 21, 2011)
  In this article we consider dependencies between virtual channels hardware implementation features and packet transmission timing parameters in a network-on-chip, as well as possibilities for different classes of services support.
  
  
• Routing Congestion: The Growing Cost of Wires in Systems-on-Chip (Feb. 21, 2011)
  This paper presents trends in technology, introduces packet based network-on-chip as a means of enabling configuration link widths, shows experimental results, and describes other benefits of packet-based interconnect networks.
  
  
• Integration Optimized SuperSpeed USB3.0 IP from Cadence - Delivering Superior Value to the SOC Designer (Feb. 14, 2011)
  Designs are moving towards a hierarchical structure, collection of individual subsystems each with a local interconnect CPU, DSP, and memory, and a global interconnect tying all these subsystems together, along with intelligent Interface IP, and multichannel memory. The pain points faced by the customer in today's world, is in obtaining and integrating enormous amount of IP, having to verify a system that comprise of SOC hardware and software, creation and validation of software, and not to mention the least, hitting schedule and budget.
  
  
• Importance of Dynamic Programming for Achieving Hard Breakdown in Anti-Fuse Technology (Jan. 31, 2011)
  As System-on-chip (SOC) developers continue to look for ways to reduce cost and time to market, it is important to consider the different non-volatile memory (NVM) options that add flexibility to their products. Over the last few years, the NVM market has been flooded with new solutions. Now, having customers weigh the benefits of reliability, options, and costs during project development is even more critical. With antifuse vendors targeting a wider range of functionality and products, noting the reliability concerns of reaching hard breakdown (HBD) compared to soft breakdown (SBD) is vital.
  
  
• 7 myths of analog and mixed-signal ASIC design (Jan. 28, 2011)
  Application specific integrated circuits (ASICs) typically conjure up the notion of massively complex logic chips containing tens or hundreds of thousands (even millions) of transistors configured to solve a customer’s unique set of problems.
  
  
• Multiband architecture for high-speed SerDes (Jan. 20, 2011)
  The authors explore a multiband architecture for a 25 Gbps SerDes, where the channel in each sub-band is approximately frequency flat, eliminating need of an equalizer in the receiver.
  
  
• How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs (Jan. 19, 2011)
  All-Digital Digital-to-Analog Converters (DACs) offer 50% lower power, 68% smaller area, process technology independence, reduced risk and cycle time, digital integration and synthesis, and easier radiation-hardened design.
  
  
• Designing an FPGA-based graphics controller (Jan. 17, 2011)
  This FPGA-based control module involves an integration of three controllers (SVGA, SDRAM, and FLASH), thereby providing additional functionality to any embedded system.
  
  
• Mixed-Signal Designs: The benefits of digital control of analog signal chains (Jan. 17, 2011)
  Mixed-signal designs combine the most powerful features and advantages of both analog and digital circuitry. One common mixed-signal architecture is a chain of analog signal blocks, each controlled by digital logic. These designs take advantage of the stability and algorithmic capabilities of digital logic to control traditional analog circuitry.
  
  
• Is there a "one-size fits all" SOC PLL? (Jan. 10, 2011)
  Like most types of circuits, there is no such thing as a "one size fits all" PLL. This article will explore the trade-offs in PLL performance and design and look for a solution to most SOC PLL needs.
  
  
• Configurable VESA - VGA and DVI Test Pattern Generator (Jan. 03, 2011)
  This paper is presented with the Video Graphics Array (VGA) and Digital Visual Interface - Digital (DVI-D) test pattern generator solution with display monitor timing specification as per the Video Electronics Standards Association (VESA) to address the VGA and DVI-D video processors RTL verification and chip validation requirements.
  
  
• Understanding the basics of PLL frequency synthesis (Dec. 27, 2010)
  Configuring a phase locked loop (PLL) for a given frequency synthesis application can simultaneously be both a quick-and easy-process as well as a time-consuming, tedious, and iterative process. This dual nature in PLL system design arises from the number of loop parameters that need to be appropriately dialed in for a given application.