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IP / SOC Products Articles

• Multi-Die SoCs Gaining Strength with Introduction of UCIe (Aug. 29, 2022)
  The Universal Chiplet Interconnect Express UCIe specification brings together very competitive performance advantages to multi-die system designers, including high energy-efficiency, high edge usage efficiency and low latency, and more. Read this article to learn all about UCIe and its many advantages for multi-die system designs.
  
  
• Implementation basics for autonomous driving vehicles (Aug. 25, 2022)
  A successful AD system implementation rests on a state-machine architecture that can formulate a truthful understanding of the environment, produce an efficient motion plan, and flawlessly perform its execution.
  
  
• What's the Difference Between CXL 1.1 and CXL 2.0? (Aug. 25, 2022)
  Compute Express Link is a high-speed interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices.
  
  
• The case for de-integrating embedded Flash (Aug. 22, 2022)
  When Flash is external to the SoC, memory is no longer a limiting factor. Developers can select a best-in-class SoC based on its performance and scale Flash density independently. Being able to right-size Flash memory also reduces system cost and footprint.
  
  
• Serial Peripheral Interface. SPI, these three letters denote everything you asked for (Aug. 18, 2022)
  This article focuses on the most important details of the modern SPI interfaces, which are improved by many useful features. But to start, let us discover the history of the modern SPI interface, because even the old, most basic SPI interfaces are still in use.
  
  
• MIPI in next generation of AI IoT devices at the edge (Aug. 08, 2022)
  One of the original benefits of processing in the cloud in was simply to expand beyond the limited capacity of on-site processing. With advancements in AI, more and more decisions can be made at the edge. It is now clear that edge and cloud processing are complementary technologies; they are both essential to achieve optimal system performance. Designers of connected systems must ask, what is the most efficient system partitioning between the cloud and edge?
  
  
• Getting started in structured assembly in complex SoC designs (Aug. 04, 2022)
  The integration level of a system-on-chip (SoC) is defined in RTL, just like the rest of the design. Historically, RTL has been built through text editors. However, a decade or more ago, the sheer complexity of that task for the largest SoCs became unmanageable; now, most SoCs cross that threshold. Why is this?
  
  
• A Generic Solution to GPIO verification (Aug. 01, 2022)
  This paper provides a complete solution to the GPIO Verification for any SoC. GPIO interface is available in every ASIC. To avoid duplicate efforts and (save) time to verify the GPIO interface, we have produced this Generic GPIO verification suite. It is a UVM-based verification environment, with all the necessary subcomponents that are required to verify any GPIO design.
  
  
• Scalability - A Looming Problem in Safety Analysis (Jul. 27, 2022)
  The boundless possibilities of automation in cars and other vehicles have captivated designers to the point that electronic content is now a stronger driver of differentiation than any other factor. It accounts for a substantial fraction of material cost in any of these vehicles.
  
  
• When Traceability Catches What Verification Does Not (Jun. 30, 2022)
  Through a complex design process, some mistakes will inevitably slip by even the most expert system-on-chip (SoC) design teams. A disciplined V-model process (diagrammed below) will guard against many of these errors in the concept-to-design process (left arm) and in the verification-to-validation process (right arm).
  
  
• Implementing C model integration using DPI in SystemVerilog (Jun. 27, 2022)
  This article gives the procedure or step-by-step guide to integrating the C model in the UVM Testbench/environment using the SystemVerilog DPI (Direct Programming Interface) feature.
  
  
• Lossless Compression Efficiency of JPEG-LS, PNG, QOI and JPEG2000: A Comparative Study (Jun. 20, 2022)
  In this paper we attempt to compare the achievable compression ratio of four lossless image formats across a data set of 2814 images exhibiting high variance in their key characteristics. The results are then categorized based on the image type to further illustrate the potential effectiveness of each image format for specific use cases.
  
  
• Understanding Interface Analog-to-Digital Converters (ADCs) with DataStorm DAQ FPGA (May. 30, 2022)
  We propose the implementation of analog signals into digital signals and data communication between the ADC and FPGA (Field Programmable Gate Array). For working on the ADC, we have used the “DataStorm DAQ” FPGA board. Designers can use any type of FPGA.
  
  
• New Ethernet Adaptation Layer Adds Control Option to MIPI A-PHY Automotive Networks (May. 19, 2022)
  To satisfy the demand for both advanced safety features and better driver and passenger experiences, automakers are adding more displays, larger in size and with greater resolutions, to the digital cockpit. This trend has created a need for more in-vehicle wiring, which in turn adds cost, weight and complexity to new car designs.
  
  
• Automotive electronics revolution requires faster, smarter interfaces (May. 19, 2022)
  In the automotive industry, features such as advanced driver-assistance systems (ADAS), connected in-vehicle infotainment (IVI) and emerging autonomous driving systems (ADS) are more important than ever, making vehicles safer and improving the driving experience
  
  
• An 800 Mpixels/s, ~260 LUTs Implementation of the QOI Lossless Image Compression Algorithm and its Improvement through Hilbert Scanning (May. 19, 2022)
  This paper discusses the hardware implementation of an encoder and a decoder for the QOI lossless RGB image format. Some results are given for the AMD/Xilinx architecture, reaching over 800 Mpixels/s in Ultrascale+ and more than 4K@30 in Artix-7. A compression improvement up to ~15% is also observed when natural images are scanned along a Hilbert curve instead of the normal raster order.
  
  
• AES 256 algorithm towards Data Security in Edge Computing Environment (May. 16, 2022)
  Today, enormous volumes of data are generated by a growing number of sensors and smart IoT devices, and ever-increasing processing power is moving the core of calculations and services from the cloud to the network's edge. Advances in Artificial Intelligence (AI) have opened up a plethora of new options for resolving security problems in the context of Edge Computing, where security and privacy have become key considerations.
  
  
• Add Security And Supply Chain Trust To Your ASIC Or SoC With eFPGAs (May. 06, 2022)
  Even though there are many security and encryption techniques designers can use to make a chip secure, what else can be done to increase the confidence that the chip is trustworthy? eFPGA opens a new range of capabilities
  
  
• Capitalizing on the Architectural Flexibility of FPGAs with RISC-V and a Simplified Programming Flow (Apr. 27, 2022)
  Microprocessors have traditionally dominated the realm of computing, and in this drive toward more compute capabilities, silicon-based ICs were consistently improved upon in device density
  
  
• CAN FD: Anything But Automotive Only (Apr. 25, 2022)
  Due to higher bandwidth requirements in the automotive field, the CAN (controller area networking) specification was extended for flexible data–rates with a new iteration known as CAN FD.
  
  
• Why Hardware Root of Trust Needs Anti-Tampering Design (Apr. 11, 2022)
  The hardware root of trust (HRoT) provides the trust base (root key), hardware identifier (UID), hardware unique key (HUK), and entropy required for the secure operation of the entire chip and therefore is often the focus of hacker attacks. If the design can’t effectively resist attacks, hackers can easily obtain the secrets of the entire chip. Attackers can use the secrets to crack identity authentication and data encryption and steal product design know-how, causing application security problems.
  
  
• Software-Defined Everything doesn't mean Software-Only Security (Apr. 04, 2022)
  Computing power has reached the point where once “hardware-only” functions can now be handled by the software layer running on top of the hardware, with negligible performance difference for users.
  
  
• TPM 2.0-Ready: Top Security with PUFcc (Mar. 24, 2022)
  The rising security threats endangering our connected world, from the chip to the cloud, are among the biggest challenges facing us today. Microsoft recently addressed some of these concerns by mandating the inclusion of TPM 2.0 (Trusted Platform Module) in all devices running its latest Windows 11 operating system. I
  
  
• Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution (Mar. 21, 2022)
  Formal verification techniques have been developed using mathematical proof rather than simulation or test vectors to provide a higher level of verification confidence on properties. For example, the implementation can be either a Verilog RTL module or an abstract version of a particular design, while the specification is typically a set of properties that needs to be verified and expressed suitably. So, formal verification provides a complete verification of each specification property under considering corner cases even without test vectors.
  
  
• UPF Constraint coding for SoC - A Case Study (Mar. 07, 2022)
  This paper deals with the implementation of UPF for low power SoC design that can encompass several vendor IPs and custom IPs UPF constraints.
  
  
• Easing PCIe 6.0 Integration from Design to Implementation (Mar. 01, 2022)
  Because of the data explosion and increasing bandwidth for high-performance computing (HPC), we are seeing PCI Express (PCIe) data rates moving from 32G (PCIe 5.0) to 64G (PCIe 6.0). In addition, since NRZ no longer supports the higher data rates, PCIe 6.0 is moving to PAM-4 signaling.
  
  
• eFPGA LUTs Will Outship FPGA LUTs Later This Decade (Mar. 01, 2022)
  FPGAs have become a strategic technology. It used to be a “poor man’s ASIC” and provided a customized IC for lower-volume applications. While it is still used this way in many systems, it has also become strategically important to two very big, high-growth applications.
  
  
• Calibrate and Configure your Power Management IC with NVM IP (Feb. 21, 2022)
  Power Management Integrated Circuits (PMICs) are the first to turn on and the last to turn off in a system. They perform the task of delivering the right voltage to component chips by regulating or boosting the voltage levels to the component chips.
  
  
• Automotive Architectures: Domain, Zonal and the Rise of Central (Feb. 17, 2022)
  Today, automotive electronics are ubiquitous, controlling or assisting with every aspect of the vehicle’s operation and performance. Electronics now account for over 40 percent of a new vehicle’s total cost, having grown from just 18 percent in 2000, according to Deloitte.
  
  
• Top 5 predictions for eFPGA in 2022 (Feb. 03, 2022)
  With the eFPGA now readily available in many process nodes from multiple suppliers, Flex Logix offers predictions on what we can expect to see around eFPGA development and use cases in 2022 and beyond.