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Fractional-N Integer LC DESKEW PLLs in FDSOI FDX (GF22FDX SS28FDS ST28FD-SOI 22FDX 28FDS)
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Magma Announces Quartz iPOP Initiative -- Delivers "Improved Productivity, Operability and Performance" for Faster, Higher Capacity Physical Verification (Monday Aug. 23, 2010)
Magma Design Automation today launched Quartz iPOP, the "improved Productivity, Operability and Performance" initiative to facilitate designers' adoption of the Quartz™ DRC and Quartz LVS software for designs targeted at 65 nanometers (nm) and below.
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Synopsys Adds TDD Support to LTE Model Library (Wednesday Aug. 11, 2010)
Synopsys today announced the availability of the Time Division Duplex (TDD) mode in its Long-term Evolution (LTE) Model Library for physical layer system simulation.
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Synopsys and Lattice Renew OEM Relationship for FPGA Synthesis Software (Wednesday Aug. 11, 2010)
Synopsys and Lattice today announced a multi-year extension of Lattice's OEM agreement for the Synopsys Synplify® FPGA synthesis tools, which Lattice has been offering to its customers for more than 10 years.
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Aldec Announces Phase-Based Linting Methodology (Monday Aug. 09, 2010)
Aldec announces ALINT™ 2010.06. The release introduces a new methodology, phase-based linting (PBL), which provides structured and prioritized phases for the analysis of HDL design issues, significantly improving development productivity and overall efficiency.
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Synopsys Galaxy Implementation Platform Used by TSMC for 28nm Process (Monday Aug. 09, 2010)
Synopsys today announced that TSMC has successfully taped out a complex 28-nanometer (nm) Product Qualification Vehicle (PQV) test chip using Synopsys' Galaxy™ Implementation Platform. Key features used to design the PQV test chip include 28-nm design rule support for place-and-route, interconnect process modeling, IEEE 1801-2009 (UPF)-based hierarchical low power flow, power-aware design-for-test (DFT) and advanced signoff capabilities.
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CriticalBlue Provides Multicore Software Development Analysis Environment for OCTEON and OCTEON II Processors (Monday Aug. 09, 2010)
CriticalBlue and Cavium Networks announced today immediate support for the OCTEON® and OCTEON II architectures within CriticalBlue's Prism software analysis, exploration and verification product. Prism can now be used by software developers building applications on multicore OCTEON and OCTEON II processors.
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Mentor Graphics Design-to-Silicon Solutions Used in Successful Development of TSMC 28nm Product Qualification Vehicle Test Chip (Monday Aug. 09, 2010)
Mentor Graphics today announced that its Calibre® Design-to-Silicon solutions were key elements in the successful development of TSMC’s 28nm Product Qualification Vehicle (PQV), a major milestone in the TSMC process development. Multiple Mentor products were used in the design of the PQV test chips, including the Calibre nmDRC and Calibre nmLVS tools for design verification, and Tessent™ test suite for silicon test.
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Magma's Quartz Physical Verification Software Used by TSMC on Complex 28-nm Product Qualification Vehicle Test Chip -- Delivers Sign-Off Accuracy Along With Required Performance and Capacity (Thursday Aug. 05, 2010)
Magma® Design Automation announced today that TSMC used Quartz™ DRC for physical verification of its 28-nanometer (nm) product qualification vehicle (PQV) test chip.
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Northwest Logic Verifies Compatibility of Its IP Cores with Aldec RTL Simulators (Monday Aug. 02, 2010)
Northwest Logic and Aldec announce that they have verified full compatibility between Northwest Logic’s IP Cores and Aldec’s RTL Simulators. Northwest Logic is a provider of high-performance, easy-to-use IP Cores, including DDR3/2, PCIe 3.0/2.0/1.1 and MIPI IP Cores. Aldec is a leading provider of RTL and gate-level mixed language Simulators, including Aldec Riviera-PRO™ 2010.06 and Active-HDL 8.3 RTL Simulators.
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SpringSoft Validates Full Interoperability of Custom Chip Design Solutions with STARC 90nm iPDK (Monday Aug. 02, 2010)
SpringSoft is among the first to complete the validation of the Japanese Semiconductor Technology Academic Research Center’s (STARC) 90nm mixed-signal reference iPDK with the SpringSoft Laker™ Custom Layout Automation System.
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Jasper DFI Formal Verification Proof Kits Now Available (Tuesday Jul. 27, 2010)
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Cadence and ARM Collaborate to Create an ARM-Optimized System Realization Solution (Wednesday Jul. 21, 2010)
Cadence today announced a broadening of its existing collaboration with ARM to develop an optimized System Realization solution for ARM processors that will enable an end-to-end flow including a full set of interoperable tools, ARM(R) processor and physical IP, services and methodology from embedded Linux to GDSII.
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DOLPHIN Integration and Infolytica Corporation enable mechatronic system simulation using MagNet and MotorSolve coupled with SMASH (Friday Jul. 16, 2010)
DOLPHIN Integration SA and Infolytica Corporation announce today that their solutions for mixed signal simulation and electromagnetic field simulation can now work together to perform powerful mechatronic system simulation.
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Arteris Adds Support for Tensilica’s Dataplane Processor Core Interface, Expanding Multi-core SOC Network-on-Chip Options (Wednesday Jul. 07, 2010)
Arteris and Tensilica today announced that Arteris' Network-on-Chip (NoC) technology for on-chip communications now fully supports Tensilica's Xtensa Processor Interface (PIF). Using Arteris' NoC technology, Tensilica's DPUs can be mixed and matched with other processor cores or RTL blocks in complex, high-throughput designs.
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DOLPHIN Integration upgrades SLED and SMASH delivering block-busting innovation (Friday Jul. 02, 2010)
Last week, Dolphin Integration delivered block-busting upgrades of their schematic editor SLED optimized with their multi-domain simulator SMASH.
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CoFluent Design and NSW launch CoFluent-On-Demand SaaS program (Thursday Jul. 01, 2010)
Japanese Users Can Adopt "Pay-as-You-Go" Licensing of ESL Modeling & Simulation Toolset CoFluent Studio through NSW Cloud Computing Infrastructure
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Next Generation Virtual Platform Simulator released by Imperas and OVP Initiative Extends Simulation Speed Advantage By 50 Percent (Tuesday Jun. 22, 2010)
Imperas today announced a major release of new technology. Highlights of this June 2010 release are the virtual platform simulator OVPsim, which has improved its industry leading performance by 50 percent; fast models of PowerPC processors, and a MIPS-based reference platform under SystemC/TLM-2.0 which boots both Linux and Mentor Graphic’s Nucleus RTOS.
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Cadence Global Services Enables Industry's First TD-LTE Baseband Chip from Innofidei (Monday Jun. 21, 2010)
Cadence Delivers First-Pass Silicon Success on the Implementation of a 65nm Low-Power Mixed-Signal SoC for China’s next-generation wireless communication protocol
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Atrenta Announces SpyGlass-Physical for Early Implementation Analysis (Thursday Jun. 17, 2010)
Atrenta announced today at the 47th Design Automation Conference the availability of the SpyGlass®-Physical product. The new addition to the SpyGlass family enables register transfer level (RTL) engineers to achieve faster design closure by modeling physical implementation effects at the RTL stage of the design.
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ARM, IBM, Samsung, GLOBALFOUNDRIES and Synopsys Announce Delivery of 32/28nm HKMG Vertically Optimized Design Platform (Tuesday Jun. 15, 2010)
ARM, IBM, Samsung Electronics, Co., Ltd., GLOBALFOUNDRIES and Synopsys today announced the delivery of the industry’s first complete vertically optimized 32/28 nanometer (nm) design platform. The solution consists of optimized high performance, low-power processor and physical IP from ARM; tool enablement, connectivity IP and integrated design flow from Synopsys; and 32/28nm low-power process technology from the Common Platform alliance of IBM, Samsung and GLOBALFOUNDRIES.
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Magillem launches CRYSTAL BULB for Advanced Platform Assessment (Monday Jun. 14, 2010)
Magillem today announces its latest offshoot Crystal Bulb for Advanced Platform Assessment. Crystal Bulb is an analysis tool of virtual platforms’ power and timing at ESL or RTL, built and validated with two major IDM players.
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Synopsys Unveils Galaxy Characterization Solution for Standard Cells, Complex Macros and Memories (Monday Jun. 14, 2010)
Synopsys today introduced its Galaxy Characterization Solution. The Galaxy Characterization Solution is a comprehensive suite of tools architected to generate compact, highly-accurate libraries for the design and implementation of complex system-on-chips (SoCs).
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Bluespec High-Level Synthesis Toolset is Selected by Fujitsu (Thursday Jun. 10, 2010)
Bluespec announced today that the Bluespec high-level synthesis toolset for development of system-on-a-chip (SoC) designs has been selected by Fujitsu Limited. It will be used for the research and design of many core processors for hardware processing embedded in the server.
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IC Manage Announces Global Design Data Management for Synopsys' Galaxy Custom Designer Solution (Thursday Jun. 10, 2010)
IC Manage today announced the integration of Synopsys’ Galaxy Custom Designer® solution and IC Manage Global Design Platform™ (GDP). Engineers can now efficiently manage and share Custom Designer’s design data across multiple design sites.
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Paradigm Works Announces SystemVerilog FrameWorks Template Generator Support for UVM (Wednesday Jun. 09, 2010)
Paradigm Works today announced that its SystemVerilog FrameWorks™ Template Generator software now supports UVM (Universal Verification Methodology).
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Oasys Design Systems’ Announces Multi-Year Strategic Chip Synthesis Technology License with Xilinx (Wednesday Jun. 09, 2010)
Oasys Design Systems today announced its multi-year strategic licensing agreement with Xilinx for Oasys’ revolutionary Chip Synthesis technology.
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austriamicrosystems adopts Nangate's Library Creator for cell library development (Wednesday Jun. 09, 2010)
Nangate and austriamicrosystems today announced that austriamicrosystems has successfully implemented the Nangate Library Creator platform to improve the productivity and cost effectiveness of its digital cell library intellectual property (IP) development.
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Avery Design Enhances Insight for Reachability Analysis, Lower Power Verification, and RT-Level DFT Analysis (Tuesday Jun. 08, 2010)
Avery Design Systems today announced its latest enhancements for Insight, the first behavioral-level, simulation-central formal analysis tool, now offering improved reachability analysis, low power verification, reset controllability analysis, and DFT analysis at the RT-level.
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Ridgetop Group Offers Breakthrough NBTI Solution Addressing Increasing IC Reliability Concerns (Tuesday Jun. 08, 2010)
Ridgetop Group announced that it has designed and patented a solution for measuring IC performance degradation caused by Negative Bias Temperature Instability (NBTI) in deep subnanometer semiconductor processes.
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Calypto Extends Industry Lead in RTL Power Optimization (Tuesday Jun. 08, 2010)
Calypto today announced the release of PowerPro 4.0, the latest version of the industry’s most advanced RTL power optimization product family. Providing sweeping improvements to PowerPro CG, PowerPro MG and PowerPro Analyzer, PowerPro 4.0 offers enhanced power optimization and usability features, enabling designers to deliver the lowest power designs possible in the shortest amount of time.