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Tiempo Unveils First Timing-Driven Design Flow for its Innovative Clockless Chip Design Technology (Monday Jun. 07, 2010)
Tiempo today announced its ability to support the use of its asynchronous IP blocks with a true timing-driven design methodology using standard SDC formats. Designers can now characterize and constrain clockless blocks in order to ensure a targeted performance.
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EVE's ZeBu Emulation System Adopted by STMicroelectronics (Monday Jun. 07, 2010)
EVE today announced that STMicroelectronics has adopted the ZeBu emulation system, including EVE’s extensive catalog of ZeBu transactors and memory models, for use in the development of 3D graphics and advanced video codec technologies.
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OneSpin Solutions Enhances 360 MV for Safe, Exhaustive 4-State X-Analysis and X-Verification (Monday Jun. 07, 2010)
OneSpin Solutions today announced that it has enhanced its flagship product 360 MV to perform 4-state X-analysis and X-verification. This enhancement enables safe, exhaustive analysis of unknown, undefined, and “don’t care” signal values (X’s) and their propagation through a design.
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Mentor Graphics Underscores Support for OVM and Extends That Support to UVM Across Multiple Products (Monday Jun. 07, 2010)
Mentor Graphics today announced it will continue to deliver comprehensive support for the Open Verification Methodology (OVM), and is extending that same level of support for the Universal Verification Methodology (UVM).
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Nangate announces integration of OpenAccess database for Library Creator Platform into LFoundry's advanced LF150 PDK (Friday Jun. 04, 2010)
Nangate and LFoundry today announced that Nangate has released an OpenAccess database integration module for the Nangate Library Creator Platform.
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Mentor Graphics Introduces Precision Rad-Tolerant Product to Provide Unique Advanced Radiation Effects Mitigation (Thursday Jun. 03, 2010)
Mentor Graphics today announced its new Precision® Rad-TolerantT FPGA design solution for aerospace and high-reliability applications. The product, developed with NASA's guidance, introduces an industry-first, synthesis-based radiation effects mitigation solution to reduce the risk of functionality problems including soft errors caused by single event upset (SEU) and single event transient (SET) disruptions. Initial support is available for SRAM, anti-fuse, and flash-based devices from Actel® and Xilinx®.
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Vennsa Technologies Sets Sights on Moving Chip Verification Beyond Debug (Thursday Jun. 03, 2010)
Vennsa Technologies today unveiled its plans to become the leading supplier of automated debugging and error localization software and simultaneously launched OnPoint™, its breakthrough verification tool for automated debugging.
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Magillem and Docea Power sign a partnership agreement: for a "power aware" platform description based on IEEE1685 (Thursday Jun. 03, 2010)
Magillem SA, the leading provider of solutions designed to reduce the global cost of complex designs and Docea Power, the Electronic System Level (ESL) company that delivers software for early power and thermal analysis, today announced they are joining their forces to work on a power aware description using IEEE 1685IP-XACT.
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Jasper Crosses the Design-to-Verification Chasm (Wednesday Jun. 02, 2010)
Jasper Design Automation, today announced new versions of ActiveDesign™ and JasperGold® with capabilities that bridge the divide between chip design and verification by sharing a common, persistent knowledge base.
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Mentor Graphics Releases 0-In CDC Version 3.0 to Support Verification Needs of Larger, More Complex Designs (Tuesday Jun. 01, 2010)
Mentor Graphics today announced the immediate availability of the 0-In® CDC tool version 3.0, the industry's most complete and effective solution for clock domain crossing verification.
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CoFluent Design Adds Embedded C Code Generation to its UML and systemC-Based Modeling and Simulation Toolset (Tuesday Jun. 01, 2010)
CoFluent Studio Offers a Unified Environment to System, Hardware and Software Engineers for Modeling and Simulating Multicore Embedded Systems and Systems-on-Chip
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XYALIS Brings Cost Reduction To Mask Design (Thursday May. 27, 2010)
XYALIS has been developing Mask Data Preparation tools in close collaboration with leading semiconductor and mask companies. This year at the Design Automation Conference XYALIS announces two new modules, to complete its proven fully integrated Mask Data Preparation solution.
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Sapiennt Systems: Powerful Software for IC Industry Decision Makers (Wednesday May. 26, 2010)
Sapient Systems today introduced Sapient-IC, the first in a line of a new class of product-management software specifically tailored to address the explosive growth in complexity and management facing decision makers in the IC industry.
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Duolog's Socrates Chip Integration Hub Supports EDA360 Vision (Tuesday May. 25, 2010)
Duolog Technologies today announced that its Socrates Chip Integration Hub supports key elements of the EDA360 vision recently unveiled by Cadence.
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SpringSoft's Laker Layout Supports TSMC 40-nm Technology with Interoperable Process Design Kit (Tuesday May. 25, 2010)
SpringSoft today announced support for the 40-nanometer (nm) interoperable process design kit (iPDK) introduced by TSMC. This builds on SpringSoft’s support of the industry’s first iPDK developed by TSMC for its 65-nanometer (nm) RF process technology.
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ARM Physical IP Production Characterization System Utilizes Magma SiliconSmart Software (Tuesday May. 25, 2010)
Magma® Design Automation announced today that ARM has successfully utilized Magma’s SiliconSmart® characterization and modeling software suite to enhance and expand ARM’s production characterization system for Physical IP products.
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Mentor Graphics Announces New FPGA Synthesis Innovation in Precision Synthesis 2010a Release (Thursday May. 20, 2010)
Mentor Graphics today announced its Precision® Synthesis 2010a product that provides a variety of enhancements, including new capabilities for mil-aero and safety-critical applications, integration with other Mentor tools, major Quality-of-Results (QoR) improvements, synthesis for lower power, and encryption based on the IEEE P1735 standard.
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Forte Unveils Cynthesizer Ultra, Next-Generation High-level Synthesis (Wednesday May. 19, 2010)
Forte Design Systems today launched Cynthesizer Ultra™, its high-level SystemC synthesis software tightly integrated with its CellMath product family to create better designs faster.
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Magma's Titan Mixed-Signal Platform Supports TSMC's 65- and 40-nm Interoperable Process Design Kits (iPDKs) (Monday May. 17, 2010)
Magma Design Automation today announced that TSMC has qualified Magma’s Titan™ mixed-signal platform to support the interoperability and accuracy requirements of the TSMC 40-nanometer (nm) Interoperable Process Design Kit (iPDK).
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ClioSoft SOS Hardware Configuration Management Platform Selected by Dongbu HiTek (Wednesday May. 12, 2010)
Dongbu HiTek of Seoul, Korea, specializing in delivering best-in-class analog and mixed signal semiconductor technologies and high value foundry services, has selected ClioSoft’s SOS™ hardware configuration management (HCM) platform to facilitate collaboration between design centers in Korea and the USA.
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OCP-IP Delivers IEEE1685 OCP Vendor Extensions (Tuesday May. 11, 2010)
OCP-IP today announced the availability of an OCP package of Vendor Extensions for IP-XACT. Vendor Extensions provide a way to fully describe the configurable OCP interface in machine-readable XML structure in an IEEE standard format. They are compatible with both IP-XACT 1.4 and IEEE1685.
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Magma's Titan Supports IPL 1.0 Standard for Interoperable Process Design Kits (Tuesday May. 11, 2010)
Magma® Design Automation announced today that the Titan™ Mixed-Signal Platform has been validated to support the interoperability and accuracy requirements of the IPL 1.0 Interoperable Process Design Kit (iPDK) standard.
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Software Developers Get New High Performance Computing C-to-FPGA Tools (Tuesday May. 11, 2010)
DRC Computer and Impulse Accelerated Technologies today announced that the Impulse C™-to-FPGA tools have been integrated with the DRC Accelium™ coprocessor card, enabling software engineers to fully access hardware acceleration using familiar C programming methods.
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Numetrics and PRTM Announce Partnership and Launch New Solution to Increase Semiconductor R&D Productivity (Monday May. 10, 2010)
Numetrics and PRTM today announced the launch of a powerful software and services solution that boosts semiconductor product development throughput—enabling semiconductor companies to significantly increase product revenue and margin. The solution was jointly developed by Numetrics and PRTM, based on a strategic partnership the two companies formed in early 2009.
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Magma Announces SiliconSmart ACE Memory Characterization -- Embedded FineSim Pro Enables Most Accurate Characterization of Timing, Power and Noise Models (Monday May. 10, 2010)
Magma(R) Design Automation today announced SiliconSmart(R) ACE Memory Characterization, the latest addition to the industry-standard SiliconSmart IP characterization and modeling product line.
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Apache Introduces PathFinder, the Industry's First Full-chip ESD Physical Integrity Solution (Monday May. 10, 2010)
Apache Design Solutions today announced PathFinder™, a full-chip electrostatic discharge (ESD) physical integrity solution to address the increasing reliability challenges faced by nanometer designs. It delivers innovative technologies in modeling, extraction, and simulation for ESD verification, targeting early prototyping, circuit optimization and full-chip signoff.
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Zocalo Tech Introduces Assertion-Based Verification Capabilities to Improve IP and Electronic Design Quality (Thursday May. 06, 2010)
Zocalo Tech today announced that it has added four new capabilities to its Zazz ™ product family. The new options simplify and support the adoption of an ABV methodology to improve electronic design and Intellectual Property (IP) quality and increase verification productivity.
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NextOp Announces BugScope Assertion Synthesis for Progressive, Targeted Verification (Thursday May. 06, 2010)
NextOp Software today announced BugScope, the industry’s first assertion synthesis product to synthesize high quality assertions and functional coverage properties from the Register Transfer Level (RTL) design and testbench.
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eASIC eTools 8.1 Design Suite Reduces Design Time by 40% (Thursday May. 06, 2010)
eASIC Corporation, a provider of NEW ASIC devices, today announced the immediate availability of its eTools 8.1 Design Suite for implementing 45nm Nextreme-2 designs. The eTools 8.1 tool suite delivers a robust ASIC grade design flow with the simplicity and ease of design that is normally associated with FPGA design tools.
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Cadence Accelerates SoC Realization, Reduces Costs With New Open Integration Platform (Wednesday May. 05, 2010)
Cadence Design Systems today announced the Cadence Open Integration Platform, a platform that significantly reduces SoC development costs, improves quality and accelerates production schedules.