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FPGA / CPLD News

• Lattice Semiconductor and Epson Toyocom Provide Low-Cost, High Frequency Differential Reference Clock Solution (Monday Oct. 12, 2009)
  Lattice and Epson today announced a low-cost reference clock solution for SERDES applications. By utilizing Lattice's ispClock(TM)5400D device and the appropriate SG-710ECK CMOS oscillator from Epson Toyocom, a designer now has a low cost reference clock for SERDES applications such as XAUI or SDI Video.
  
  
• Xilinx Spartan-6 FPGAs Enable PCI Express Compliant System Design for Low-Power, Low-Cost Connectivity Applications (Monday Oct. 05, 2009)
  Xilinx today announced that its low-cost Spartan®-6 FPGA family is compliant with the PCI Express® 1.1 specification, enabling low-risk and low-cost implementation of serial connectivity solutions for consumer, automotive, wireless, and other price-sensitive or high volume markets.
  
  
• Altera's Stratix IV GX FPGAs Move to Volume Production (Wednesday Sep. 23, 2009)
  Altera Corporation (NASDAQ: ALTR) today announced it is shipping volume production of its 40-nm Stratix® IV GX EP4SGX230 FPGAs. The Stratix IV device was the industry's first 40-nm FPGA available when it began shipping at the end of 2008 and it continues to lead the market as the only 40-nm FPGA in volume production.
  
  
• New Firmware Catalog Enhances Actel's Tool Suite for Embedded Software Developers (Monday Sep. 21, 2009)
  Actel continues its commitment to enhancing the embedded processor development tool suite with the release of its new Firmware Catalog. This new tool streamlines the locating and generating of firmware that is compatible with Intellectual Property (IP) cores used in Actel embedded processor based low-power IGLOO®, ProASIC®3 or Fusion mixed-signal FPGA designs.
  
  
• Achronix Unveils 120 Gbps Reprogrammable Networking System (Wednesday Sep. 16, 2009)
  Achronix Semiconductor today announced the availability of Bridge100, a 120 Gbps Infiniband-to-Ethernet programmable platform designed to put high-performance capability into the hands of communications systems designers.
  
  
• Micrium Offers Expanded Support for uC/OS-II RTOS for Entire Tensilica Dataplane Processor Line (Wednesday Sep. 16, 2009)
  Tensilica and Micrium announced expanded support for Micrium's popular uC/OS-II RTOS (real-time operating system) available directly from Micrium. The RTOS port has been enhanced to take full advantage of all configuration options on Tensilica's Xtensa® customizable dataplane processors (DPUs) as well as Tensilica's standard DPUs and Diamond controller cores.
  
  
• Xilinx Extends Next Generation Serial Connectivity Portfolio from Low-Cost Systems to 100 Gigabit Applications and Beyond (Wednesday Sep. 16, 2009)
  Xilinx today announced design support for Virtex(R)-6 HXT FPGAs with the 11.3 release of the ISE(R) Design Suite software. Optimized for 40G/100G wired telecommunications and data communications, Virtex-6 HXT FPGAs deliver serial interface technology to designers of ultra-high bandwidth systems with line rates in excess of 11 Gigabits per second (Gbps).
  
  
• Altera Extends Its Technology Leadership with the 820K-LE Stratix IV FPGA (Monday Sep. 14, 2009)
  Latest Member of the Stratix IV FPGA Series is the Industry's Highest Density FPGA, Offering Highest Performance and Lowest Power in Its Class
  
  
• Xilinx FPGAs Enable TeamCast Digital TV and Mobile TV Modules for Professional Broadcast Systems (Friday Sep. 11, 2009)
  Virtex and Spartan FPGAs Provide Flexibility, Logic Capacity, and Embedded Processing for TeamCast Multi-standard Modulation Product Portfolio
  
  
• Lattice Semiconductor Updates Guidance for Third Quarter 2009 (Friday Sep. 11, 2009)
  Lattice today announced updated guidance for the third quarter ending October 3, 2009. Third quarter revenue is now expected to be approximately flat to up 3% sequentially.
  
  
• Xilinx Demonstrates New Broadcast Offerings That Lower Cost and Power of Serial Digital Interfaces (Tuesday Sep. 08, 2009)
  Xilinx today announced demonstrations of the latest developments in serial connectivity that lower the cost and power of serial digital interfaces and enable the rapid adoption of emerging DisplayPort and Ethernet AVB protocols.
  
  
• Dolby Digital Professional Encoder Now Available on Xilinx FPGAs for High Performance, Low Power Audio Broadcast Applications (Tuesday Sep. 08, 2009)
  Xilinx collaborated with Coreworks S.A., a leading provider of reconfigurable multimedia and communications intellectual property (IP) blocks, to port and certify the Dolby Digital 5.1 channel professional encoder in Virtex-5 FPGAs. This solution will also be provided on the latest generation of high performance Virtex-6 and low-power, low-cost Spartan(R)-6 FPGAs.
  
  
• Lattice Delivers Low Cost and Convenience to Designers of Consumer Products (Tuesday Sep. 08, 2009)
  Lattice today announced the immediate availability of eight new reference designs, a $49 development kit for the ProcessorPM(TM) POWR605 power manager device and a $69 development kit for the ispMACH(R) 4000ZE CPLD, the ispMACH 4000ZE Pico Development Kit.
  
  
• Actel Announces Availibility of RTAX-DSP Prototype FPGAs (Tuesday Sep. 01, 2009)
  Actel today announced the availability of RTAX-DSP prototype FPGAs, enabling hardware demonstration and timing validation of designs targeted to Actel's RTAX-DSP space-flight FPGAs.
  
  
• Configurable Advanced Touch-Screen LCD Video Evaluation Platform Now Available for Lattice FPGA Families (Monday Aug. 31, 2009)
  Lattice today announced the release of LCD-Pro, an advanced FPGA-based LCD video imaging and control solutions platform. Developed by Lattice partner Exor International, the LCD-Pro evaluation platform is based on the low-cost LatticeECP2(TM) and LatticeXP2(TM) FPGA devices, and the UltiLogic family of graphics Intellectual Property (IP) Cores from Exor International.
  
  
• LatticeECP3-150 FPGA Delivers Unprecedented Value for Wireless and Wireline Applications (Monday Aug. 24, 2009)
  Lattice Semiconductor today announced that samples of the LatticeECP3(TM)-150 FPGA, the highest-density device in its high-value, low-power ECP3 mid-range FPGA family, are now generally available. Samples have already been shipping to select customers since July of this year.
  
  
• Lattice Announces Updated, More Accessible CPLD Design Tools (Monday Aug. 03, 2009)
  Lattice today announced the immediate availability of Version 1.3 of its ispLEVER® Classic design tool suite. Version 1.3 includes updated support for Lattice CPLDs (Complex Programmable Logic Devices), including the widely popular ispMACH® 4000 device family.
  
  
• Actel's Libero IDE v8.6 Continues to Lead the Way in Low Power Design and Analysis (Monday Aug. 03, 2009)
  Actel continues to lead the way for low-power designs with the release of Libero® Integrated Design Environment (IDE) v8.6. The newest version of the Libero IDE offers designers several new features, including upgraded power analysis using the SmartPower tool and post-layout probe insertion for device debug.
  
  
• Altera Extends Temperature Range of Stratix III FPGAs to Support Military Applications (Wednesday Jul. 29, 2009)
  Altera Corporation today announced it has extended the temperature range for selected members of its Stratix® III FPGA family to support military applications operating in rugged environments.
  
  
• Altera's 40-nm Arria II GX FPGAs Achieve PCI-SIG Compliance for PCIe Express 2.0 Specification (Tuesday Jul. 28, 2009)
  Altera Corporation today announced its 40-nm Arria® II GX FPGAs are compliant with the PCI Express® (PCIe®) 2.0 specification. Currently shipping, Altera's mid-range Arria II GX FPGAs feature integrated transceivers with data rates up to 3.75 Gbps, and have a hard, configurable PCIe interface embedded within the device
  
  
• Xilinx Virtex-6 FPGAs Enable Highest PCIe Bandwidth for Mainstream Applications With Compliant PCI Express 2.0 Endpoint (Monday Jul. 27, 2009)
  Xilinx today announced that its Virtex -6 FPGA family is compliant with the PCI Express 2.0 specification, delivering up to 50 percent lower power than previous generations and 15 percent higher performance than competitive offerings.
  
  
• Altera Speeds Development of High-Performance 3-Gbps Applications With Arria II GX Development Kit (Monday Jul. 27, 2009)
  Altera today announced availability of the Arria® II GX FPGA Development Kit. The kit features hardware and software resources that enable customers to rapidly evaluate and adopt Arria II GX devices, Altera's mid-range 40-nm FPGAs.
  
  
• FPGA startups stare down giants and ghosts (Monday Jul. 27, 2009)
  Cswitch Corp. made waves and headlines in 2006 when it unveiled a novel configurable array architecture said to be capable of narrowing the performance and density gaps between field-programmable gate arrays and application-specific ICs.
  
  
• Altera's Stratix IV GX FPGAs Deliver Unprecedented Performance for Sumitomo Electric Industries' LDPC System (Monday Jul. 13, 2009)
  Altera today announced Sumitomo Electric Industries, Ltd. is leveraging 40-nm Stratix® IV GX FPGAs in an advanced low-density parity-check (LDPC) system.
  
  
• Actel's Mixed-Signal Power Manager Provides Complete Graphical Design Approach for Fusion Mixed-Signal FPGAs (Monday Jul. 13, 2009)
  Actel today announced the availability of its free Mixed-Signal Power Manager (MPM). A reference design and graphical user interface (GUI) tool included in the recently announced Fusion Advanced Development Kit, MPM enables designers to control and reduce power at the system level, offering fully-verified, timing-closed, proven-in-hardware power supervision and management capabilities.
  
  
• Actel Now Shipping the Fusion Advanced Development Kit (Monday Jul. 13, 2009)
  Actel today announced that it is shipping the Fusion Advanced Development Kit. Featuring Actel Fusion® mixed-signal FPGAs, the kit enables the development of system and power management applications in a single board with multiple on-board voltage regulators, an array of indicator LEDs, and an OLED display to provide direct feedback on flag status, system messages, and voltage, temperature, or current readings.
  
  
• Altera Announces New Cyclone III LS FPGAs (Monday Jun. 29, 2009)
  Altera today announced a new low-power FPGA family with security features. The new Altera® Cyclone® III LS FPGAs offer the highest logic, memory, and DSP density per board area.
  
  
• New Package Option for Lattice MachXO PLD Family Reduces Cost and Board Area (Monday Jun. 29, 2009)
  Lattice today announced the immediate availability of a new 0.8-mm pitch 256-pin Chip-Array BGA (caBGA256) package for its popular MachXO™ PLD family that provides designers with a broader range of package options for implementing cost-sensitive, board space constrained designs.
  
  
• Xilinx Accelerates Development of Next-Generation Systems With Industry's First Deployment of Targeted Design Platforms (Wednesday Jun. 24, 2009)
  Xilinx today released the Xilinx Base Targeted Design Platform aimed at accelerating the development of system-on-chip (SoC) solutions with Xilinx(R) Virtex(R)-6 and Spartan(R)-6 field programmable gate arrays (FPGAs).
  
  
• SiliconBlue Launches "Turbo" Speed Version of Ultra-Low Power iCE65 mobileFPGA Family (Monday Jun. 15, 2009)
  SiliconBlue today announced availability of a new, high-speed, “turbo” option for its iCE65™ mobileFPGA™ family. Built using TSMC’s 65nm low power CMOS process, the 65% faster speed grade addresses a growing requirement in consumer mobile applications where higher speed logic solutions in battery-based handheld applications are necessary.