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IP / SOC Products News

• Virage Logic's AEON(R) Becomes the First Multi-Time Programmable Embedded Non-Volatile Memory Available on a Standard CMOS Process Qualified to Rigorous Automotive Standard AEC-Q100 (Tuesday Jun. 23, 2009)
  Virage Logic today announced its AEON(R) multi-time programmable (MTP) non-volatile memory (NVM) solution is the first qualified to the stringent quality and reliability standards of the automotive industry using only standard CMOS processing.Automotive integrated circuits (ICs) demand reliability and qualification testing above and beyond the requirements of typical consumer or industrial applications.
  
  
• Dolphin Integration puts in the public domain a unique freeware for evaluation of Standard Cell libraries (Monday Jun. 22, 2009)
  Dolphin Integration announces the release of Motu Uta, a flexible logic circuit designed for being representative of complex logic designs. With Motu Uta, the company expects to speed-up the introduction of its innovative libraries of standard-cells and to help its potential users to reach in the shortest lead-time a conclusion on the benefit of its library stems versus contenders.
  
  
• Tensilica Announces High-Performance ConnX Baseband Engine for LTE and 4G Wireless DSP Handsets and Base Stations (Monday Jun. 22, 2009)
  Tensilica today announced the first member of its new ConnX family of digital signal processor (DSP) cores for system-on-chip (SOC) design. The ConnX Baseband Engine enables efficient baseband processing for 3G, LTE (Long-Term Evolution) and 4G wireless equipment with its scalable, high-performance DSP architecture that provides industry leading computational throughput of 16 18-bit MACs per cycle.
  
  
• VinChip Announces India's First Homegrown 32-Bit RISC Processor (Friday Jun. 19, 2009)
  VinChip Systems announces the immediate availability of its convergent 32-bit RISC processor, VinRZ5110. Its DSP enhanced instruction set architecture, low power design and optimized gate count makes it well suited for DSP and other embedded applications.
  
  
• ARM Mali GPUs Achieve Industry-Firsts With Khronos OpenGL ES 2.0 Conformance For 1080p and Multicore (Tuesday Jun. 16, 2009)
  ARM® Mali™ graphics processing units (GPUs) demonstrate technology leadership in graphics acceleration through conformance to the Khronos OpenGL ES 2.0 API with two industry milestones.
  
  
• Innovative Logic announces fully integrated USB3.0 Controller with PCS layer (Tuesday Jun. 16, 2009)
  Innovative Logic announced today the second release of USB 3.0 Device Controller IP. Inno-Logic’s USB3.0 IP offering includes implementation IP as well as verification IP by making use of industry standard latest tools and methodologies.
  
  
• Noesis Technologies Releases Fully Configurable Interleaver-Deinterleaver IP (Friday Jun. 12, 2009)
  Noesis Technologies announced today the availability of its new version of a fully configurable Interleaver-Deinterleaver IP core. The ntINT_DEINT is a fully configurable interleaver-deinterleaver compliant to a variety of industry standards such as DVB, ATSC, IEEE 802.16 e.t.c.
  
  
• Gennum's Snowbush IP Group Delivers the Industry's First PCI Expess 3.0 PHY IP on TSMC 40nm Process (Monday Jun. 08, 2009)
  Gennum today announced that its Snowbush IP group has developed the industry’s first available integrated PCI Express® 3.0 (Gen 3) PHY and Controller IP solution. The new PCIe® 3.0 cores can be licensed immediately by system-on-a-chip (SoC) and system companies, enabling early deployment of PCIe 3.0 (Gen 3) in systems requiring the 8.0 Gigatransfers per second (GT/s) performance of this new PCI-SIG standard. PCIe 3.0 opens up more bandwidth using the same physical connectors and adds new features to improve the user experience in server network and computer products using PCI Express.
  
  
• CAST Expands Video IP Cores Line with New Video Deinterlacer (Thursday Jun. 04, 2009)
  The new core converts incoming interlaced video to progressive video format for further processing or display. It accepts an industry- standard 8-bit ITU-R BT.656 video stream for wide compatibility, and its lean processing means it requires little ASIC or FPGA area and causes practically no video transmission delay.
  
  
• Synopsys Announces First DDR3 IP Verified in Silicon at 1600 Megabits per Second (Wednesday Jun. 03, 2009)
  Synopsys today announced that its DesignWare® DDR3/2 PHY and digital controller IP is the first DDR3 IP that has been fully verified in test silicon at 1600 Megabits per second (Mbps), the maximum data-rate of the JEDEC DDR3 specification.
  
  
• Palmchip Stimulates Economic Recovery by Offering Free Semiconductor IP Cores (Tuesday Jun. 02, 2009)
  Palmchip today announced the launch of their “SoCStart” IP Program providing free semiconductor IP cores. The company is also announcing the AcurX-51™, a SoC platform with integrated 8051 core. Designers can use this SoC platform to quickly start their SoC chip project. AcurX-51 is ported into Xilinx FPGA for rapid firmware and software development.
  
  
• Socle Partners with Catena, CoreSonic to Drive Wireless SoC Platform in 65nm as Mobile Solution (Monday Jun. 01, 2009)
  Socle Technology today announced its partnership with Catena and CoreSonic to develop a comprehensive design platform on Chartered’s 65nm process with integrateable wireless subsystems. Socle contributes its integrated and silicon-proven ARM9 and ARM11 design platforms. Catena provides its wireless subsystems for WiFi, WiMAX, and GPS functions, and CoreSonic offers its proven Wifi/WiMax baseband IP.
  
  
• C80186EC IP Core Added to the Evatronix 80186 Replacements Family (Monday Jun. 01, 2009)
  Evatronix announced today the release of the 80186EC IP core – a 16-bit microprocessor compatible with the 80c186ec chip from Intel®. The core implements a wide set of peripherals to address a variety of possible applications.
  
  
• Radiocomp releases their CPRI v4.0 compliant IP core for LTE, WCDMA, CDMA and WIMAX supporting speeds up to 6.144 Gbps independently from the selected silicon technology (Thursday May. 28, 2009)
  To enable higher performances and carrier grade capacity for multi-standard radio access networks Denmark based Radiocomp today released their CPRI v4.0 compliant IP core for LTE, WCDMA, CDMA and WIMAX supporting speeds up to 6.144 Gbps independently from the selected silicon technology. The compact and market-proven CPRI v.4.0 IP core has been adopted by companies such as Altera, mimoOn and Toshiba.
  
  
• Sarance Announces Availability of Complete Connectivity Solutions for Netronome's Network Flow Processors (Thursday May. 28, 2009)
  Sarance Technologies announced today the immediate availability of a complete connectivity solution for Netronome’s NFP-32xx family of Network Flow Processors™. The solution uses Sarance’s Interlaken IP Core (IIPC) products targeted for Field Programmable Gate Arrays (FPGAs) and provides a risk free solution for system developers using the NFP.
  
  
• Start-up claims breakthrough in reconfigurable logic (Thursday May. 28, 2009)
  A British company focused on dynamically reconfigurable logic technology, Akya (Selby, England), has launched its first device, dubbed the ART2.
  
  
• MindTree Lists Bluetooth Health Device Profile (HDP) (Thursday May. 28, 2009)
  MindTree today announced that its Bluetooth Health Device Profile (HDP) along with its EtherMind 2.1+EDR stack have been successfully listed as a qualified design component by the Bluetooth Special Interest Group (SIG).
  
  
• Synopsys Releases DesignWare SATA IP for New SATA 6Gbps Data Transfer Rate (Wednesday May. 27, 2009)
  Synopsys today announced the availability of DesignWare® SATA AHCI host and device digital controller IP for the latest SATA 6 Gigabit per second (Gbps) data transfer rate as defined in the Serial ATA (SATA) Revision 3.0 specification.
  
  
• Rambus Unveils New Innovations for Main Memory (Tuesday May. 26, 2009)
  Rambus today unveiled a set of innovations that can advance computing main memory beyond current DDR3 data rate limits to 3200Mbps. These innovations, available for licensing, build on Rambus’ award-winning designs and include patented and patent pending technologies.
  
  
• CEVA and mimoOn to Collaborate on Development of LTE Baseband Solutions (Tuesday May. 26, 2009)
  CEVA and mimoOn today announced a collaboration to offer mimoOn's mi!MobilePHY™ advanced LTE software on CEVA's newest DSP core, the CEVA-XC™.
  
  
• IP Cores from Eureka Technologies Validated for Mentor Graphics' Precision FPGA Synthesis (Thursday May. 21, 2009)
  Eureka Technology has validated its NAND Flash controller, Secure Digital (SD, SDIO) and Multimedia Card (MMC) host and device controller IP cores for use with Mentor Graphics’ Precision® Synthesis FPGA flow. Designers can now use the advanced features of Precision Synthesis to achieve superior results with Eureka Technology’s IP cores for multiple FPGA device vendors.
  
  
• Unity Semiconductor, a Non-Volatile Memory Products Start-up, Exits Stealth Mode; World's First R/W Cross-Point Memory Array Requires No Transistor in Memory Cell (Thursday May. 21, 2009)
  The storage-class non-volatile memory (NVM) products company plans to achieve its objective using innovative, multi-layer, memory array architectures and a new breakthrough technology called CMOxTM, which is based on the use of new materials called conductive metal oxides into the semiconductor process that allows for ionic motion.
  
  
• Virage Logic Introduces First Commercially Available Multi-Time Programmable Non-Volatile Memory Solution at 65-Nanometer Low Power (Wednesday May. 20, 2009)
  Virage Logic today announced it has qualified its AEON(R) non-volatile memory (NVM) solution on TSMC's 65-nanometer (nm) Low Power (LP) process. As the industry's first multi-time programmable (MTP) logic NVM solution that is commercially available on a 65nm process, AEON further extends Virage Logic's NVM provider leadership position.
  
  
• GDA Technologies to Demonstrate 'Pravega' Family of Configurable USB 3.0 Controllers (Wednesday May. 20, 2009)
  GDA announced today to demonstrate "Pravega"--its USB 3.0 family of cores consisting of a highly configurable Superspeed device, hub and host controllers that are interoperable with third party PIPE compatible USB 3.0 PHY's running at 5 Gbits/s maximum speeds.
  
  
• eMemory Announces Availability of Low Cost OTP Mass Production Solution - NeoROM (Wednesday May. 20, 2009)
  eMemory today announced the roll-out of NeoROM, a powerful one-time programmable (OTP) solution for products in mass production.
  
  
• WideSail Technologies announces availability of their 10 Gb Ethernet FEC Decoder (Wednesday May. 20, 2009)
  WideSail announces general availability of their new NIAGARAflow LDPC error correcting decoder core for 10 GbE. This core outperforms the competition in every metric including power consumption, throughput, latency and output Bit Error Rate. It is compliant with the 10 GbE standard (IEEE 802.3an) but can also be adapted to many other similar applications.
  
  
• CEVA and Aricent to Demonstrate LTE PHY Platform for Cellular Handsets (Monday May. 18, 2009)
  CEVA and Aricent announced today that the companies will demonstrate a licensable IP platform for LTE baseband terminals based on a CEVA DSP core. The platform will showcase a CEVA DSP running several LTE physical layer functions purely in software.
  
  
• LogicVision Delivers Power-Aware Memory Self-Repair (Friday May. 15, 2009)
  LogicVision today announced a new power-aware version of its ETMemory™ built-in self-repair solution. On-chip memory test and repair is now fully compatible with the increasingly popular power management approach of using voltage islands to minimize power during functional operation.
  
  
• Synopsys Demonstrates DesignWare SuperSpeed USB 3.0 Controller IP at the SuperSpeed USB Developer's Conference (Thursday May. 14, 2009)
  Synopsys today announced its DesignWare® SuperSpeed USB 3.0 digital controller IP has tested successfully for interoperability with Texas Instrument's (TI) SuperSpeed USB 3.0 transceiver
  
  
• Enable Customers' Fastrack to USB 3.0, Faraday Pioneers to Launch Its USB 3.0 PHY in UMC 0.13um (Thursday May. 14, 2009)
  Faraday today announced the availability of the commercial USB3.0 physical layer (PHY) at UMC 0.13um high-speed (HS) process. This new component is based upon USB 3.0 version 1.0 specification, functionally and electrically, with the maximum speed of 5.0Gbps.