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IP / SOC Products News

• MOSAID to Unveil Enhanced Flash Architecture for Solid State Drives (Tuesday Jul. 29, 2008)
  MOSAID's HLNAND(TM) Flash is a new architecture and interface for high-performance Flash memory.
  
  
• Vivante's OpenGL ES 2.0 Conformance Submission First to Support Depth Texture Extension (Monday Jul. 28, 2008)
  Vivante has submitted conformance results based on the GC600 2D/3D GPU IP core for the OpenGL ES 2.0 conformance test to the KhronosTM Group for review.
  
  
• MIPS Technologies' Silicon-proven GPS RF Tuner IP Reduces Risk for Developers of Next-generation Devices with GPS (Monday Jul. 28, 2008)
  The silicon-proven, integrated low-noise RF front-end for GPS receivers in the L1 band enables embedded system designers to decrease costs and time-to-market for next-generation devices incorporating GPS.
  
  
• Synopsys Announces Availability of New Fully Synthesizable PowerPC Cores (Wednesday Jul. 23, 2008)
  Synopsys today announced the availability of fully synthesizable implementations of the IBM PowerPC® 460 and cache configurable PowerPC 405 embedded microprocessor cores as components of the DesignWare® Star IP program.
  
  
• DOLPHIN Integration launches the 32-bit challenger: FlipAPS-32, a processor tiny enough for embedding controls (Monday Jul. 21, 2008)
  Dolphin Integration and Cortus SA are partnering for this 32-bit processor with the silicon area of a 16-bit core and with a minimal power consumption, but with the largest addressing capability.
  
  
• Denali Announces New LPDDR2 Memory Controller and PHY Solution (Monday Jul. 21, 2008)
  First Provider of Memory Controller and PHY Solution to Support LPDDR2 in Next-Generation Mobile and Embedded Applications
  
  
• Algotronix adds thermal signaling to IP core DesignTag (Friday Jul. 18, 2008)
  Algotronix has added 'thermal signaling' to DesignTag, an active digital circuit element that can be designed-in to ICs and FPGAs and detected through-package by an external scanner.
  
  
• eInfochips announces SPI4.2 and CCIR656 Stream Generator Design IP (Friday Jul. 18, 2008)
  eInfochips today announced the availability of OIF (Optical Internetworking forum) compliant SPI4.2 design IP (System packet interface Level 4 Phase 2) and ITU-R BT 601 and ITU-R BT 656 compliant CCIR 656 stream generator design IP.
  
  
• Digital Blocks Announces I2C-Master Controller IP Core Family with the availability of the DB-I2C-M for the ARM AMBA 2.0 APB and Altera NIOS II Avalon Interconnects (Friday Jul. 18, 2008)
  The DB-I2C-M targets High-Performance Embedded Processor designs requiring a Smart I2C Controller in a small VLSI footprint
  
  
• Athena Announces Cryptographic-Grade Random Number Generator (Tuesday Jul. 15, 2008)
  Portable to any semiconductor process, Athena's TeraFire RNG cores are a fast and reliable way to incorporate cryptographic-grade random numbers into your SoC design.
  
  
• Synopsys Broadens DesignWare SATA Solution With Device IP (Monday Jul. 14, 2008)
  Comprehensive SATA IP Portfolio Including Device, Host, PHY and Verification IP Passes Interoperability Testing, Reducing Integration Risk for SoC Designs
  
  
• Silicon Image Offers Mobile Phone Manufacturers a Better Way to Implement an HDTV Connection (Monday Jul. 14, 2008)
  Silicon Image today announced its ultra-low-power interface solution consisting of a VastLane(TM) SiI9206 HDMI(TM) transmitter PHY semiconductor and a companion link layer IP core for use in consumer mobile device applications.
  
  
• ARM Mali-200 GPU World's First To Achieve Khronos OpenGL ES 2.0 Conformance At 1080p HDTV Resolution (Monday Jul. 14, 2008)
  The ARM® Mali™-200 graphics processing unit is the first GPU on today’s market to pass Khronos conformance testing at up to 1080p HDTV resolutions.
  
  
• Virage Logic Expands Memory Interface Product Portfolio With New DDR3 Solution That Supports Speeds Up to 1.6 Gb/s (Monday Jul. 14, 2008)
  Comprising a DRAM memory controller, digital PHY, DLL, and I/O, Intelli DDR3 provides a true System Aware IP(TM) solution that is able to mitigate and manage the high-speed interconnect effects that must be addressed at the package as well as board level.
  
  
• A New Era for Dolphin Integration's Embedded Memories (Monday Jul. 14, 2008)
  Dolphin Integration is announcing a blockbuster sRAM Trio for embedding in circuits at 130 nm in G process and at 90 nm in LP process.
  
  
• Chips&Media unveils Boda7503, High-Definition video IP solution including AVS (Friday Jul. 11, 2008)
  Chips&Media’s Boda7503 is a highly optimized decode core supports H.264, MPEG-2, MPEG-4, VC-1, RealVideo, MJPEG in addition to AVS up to HD(1080p).
  
  
• Cambridge Consultants XAP5 core sets new standard for 16-bit processors (Thursday Jul. 10, 2008)
  XAP5 combines the economy of a 16-bit data word with a 24-bit address space for large programs up to 16 Mbytes, which suits devices designed for data-centric communications applications in markets such as consumer, industrial and retail.
  
  
• Dolphin Integration announce a breakthrough in silicon IP for power management (Monday Jul. 07, 2008)
  SRO and SRI Switching Regulators innovate with their inductorless architecture, a technique used for the first time in silicon IP.
  
  
• Evatronix adds 6502 and 80186XL ISA-compliant IP cores to its portfolio (Monday Jul. 07, 2008)
  Both solutions add up to Evatronix obsolete part replacement IP core family.
  
  
• Sonics Eliminates Barriers to Multichannel Memory Management Industry Adoption With New Interleaved Multichannel Technology(TM) (Tuesday Jul. 01, 2008)
  IMT utilizes an innovative memory interleaving methodology as a foundation for managing up to 8 external DRAM channels. User-controlled interleaving addresses the key challenge of adopting multichannel architectures: ensuring that the memory traffic is divided evenly among the channels.
  
  
• New SonicsSX SMART Interconnect Solution Solves Memory Performance Problem for High Quality, High Definition Video SoCs (Tuesday Jul. 01, 2008)
  Designed for SoCs requiring high quality, high definition, or HQHD, video support, SonicsSX accelerates video performance and eases global integration of intellectual property cores and subsystems onto a single chip.
  
  
• MoSys Demonstrates Blu-Ray Solution for Home Entertainment Applications (Tuesday Jul. 01, 2008)
  The MoSys solution is the first in the industry to support all next-generation Blue-Laser and current Red-Laser DVD formats in a single, integrated design for multi-format DVD players and recorders, game consoles, PCs, advanced Set-Top boxes, and digital video recorders.
  
  
• Lattice Enhances its Wireless Base Station Solutions Portfolio (Monday Jun. 23, 2008)
  Lattice Semiconductor Corporation today announced the availability of three new Intellectual Property (IP) core and reference design products targeting the wireless communications market.
  
  
• Kaben Wireless Silicon releases high-performance frequency synthesizer for WiMAX applications (Tuesday Jun. 17, 2008)
  The Fractional-N synthesizer delivers a -116 dBc/Hz phase noise performance and -90 dBc spurious response at 6 GHz output
  
  
• IP Cores, Inc. Shipped Ultracompact AES and AES/GCM IP Cores for Actel FPGA Supporting FIPS-197, IEEE 802.1AE MACsec and P1619.1 Standards (Monday Jun. 16, 2008)
  Starting at 800 tiles for AES1-8E and delivering 11.2 Mbps on RTSX radiation-tolerant devices, AES and AES/GCM cores provide a compact and high-performance solution for an FPGA designer working on a secure communication solution.
  
  
• Virage Logic Unveils One Mega-Bit Embedded Reprogrammable Non-Volatile Memory (NVM) on Standard CMOS Process (Monday Jun. 16, 2008)
  Combining user-defined functionality with Virage Logic’s high-capacity read-only memory (ROM) and NOVeA® Flash memory, emPROM provides secure, fully integrated embedded NVM for SoC designs requiring up to 16 Megabits of code storage and is manufactured on industry standard CMOS processes with no additional mask or process steps.
  
  
• Radiocomp & Altera partner on OBSAI/CPRI cores (Thursday Jun. 12, 2008)
  Denmark-based Radiocomp and Altera Corporation today announced an integrated, rapid development solution for developers of WiMAX and 3GPP LTE base station equipment.
  
  
• Faraday Announces the First Commercially Available 1GHz Memory Compiler to Enable GHz CPU & SoC Designs in UMC 90nm (Thursday Jun. 12, 2008)
  The single-port memory compiler utilizes advanced layout and circuit design techniques to provide up to 1GHz speed and keeps the same power and area requirement as generic memory solutions.
  
  
• austriamicrosystems further expands field-programmable OTP memory portfolio for its advanced 0.35um process family (Thursday Jun. 12, 2008)
  The polyfuse-based OTP memory cell “PPROM” is available in two fixed sizes of 4x8 bit and 16x8 bit and comes with a parallel interface. It is accessible like a static RAM and offers direct addressed outputs. The “PPTRIM” blocks available in sizes of 8 bit, 16 bit, 32 bit, 48 bit and 64 bit offers a three wire interface and auto-load at poweron reset.
  
  
• Synopsys Announces DesignWare IP for PCI Express with PCI-SIG I/O Virtualization Technology (Wednesday Jun. 11, 2008)
  The PCI-SIG I/O Virtualization (IOV) technology, which builds on the PCI Express (PCIe) protocol stack, reduces the system hardware requirements by enabling the simultaneous sharing of peripherals across multiple CPUs or operating systems.