IP / SOC Products News
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Arasan Chip Systems PCI Express Gen2 Solution Named to PCI-SIG Integrators List (Thursday Jun. 05, 2008)
New Flexible PCIe IP Core and Development Platform Passes Rigorous Interoperability and Compliance Testing
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Evatronix enhances its Ethernet MAC product line with MAC-1G PCS IP core (Thursday Jun. 05, 2008)
Physical Coding Sublayer (PCS) add-on to the successful MAC-1G controller provides new opportunities for an already wide range of possible implementations.
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Imagination Technologies Extends Low-Power Receiver IP Platform (Thursday Jun. 05, 2008)
Imagination Technologies announced today that it has added NorDig-Unified 1.0.3.compliant DVB-T to its licensable receiver IP platform family.
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Virage Logic Supports TSMC's Power Trim Service(TM) for Advanced Process Nodes (Tuesday Jun. 03, 2008)
With its advanced tradeoff capabilities, SiWare Memory users can achieve static power savings of up to 35 percent, 70 percent or 90 percent depending on their selection of the built-in light sleep, deep sleep and shut-down modes available in 40nm memories.
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Virage Logic Delivers Open RTL to Test Floor Embedded Memory Test and Repair Subsystem (Monday Jun. 02, 2008)
New Release of STAR Memory System Expands Availability of Subsystem Beyond Virage Logic Memories to Third-Party and Internally Developed Memories
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ARM Mali-400 MP Technology Brings High-end Graphics to all Consumer Devices (Monday Jun. 02, 2008)
ARM today announced the ARM® Mali™-400 MP scalable multiprocessor graphics solution, capable of delivering performance of up to 1G pixels per second and enabling licensees to serve multiple product markets with the same architecture, whilst retaining the flexibility to choose the optimum power, performance and area configuration for their application.
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Xilinx Meets Performance Requirements of LTE Wireless Systems With New LogiCORE Turbo Encoder and Decoder Solutions (Friday May. 30, 2008)
The new Xilinx 3GPP LTE Turbo Encoder and Decoder LogiCORE(TM) offerings deliver throughput speeds of up to 200 Mbps with the embedded digital signal processing (DSP) capabilities of Spartan(R) and Virtex(R) field programmable gate arrays (FPGAs)
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Denali First to Release Full DDR3 DIMM IP Solution (Thursday May. 29, 2008)
This new DDR3 DIMM offering adds unique capabilities in the memory controller and PHY IP that are needed for networking, storage and personal computing systems using DDR3 modules at data rates up to 12.8GBytes/s per DIMM.
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DapTechnology announces VHDL Testbench for its FireLink Extended 1394b link layer controller IP Core (Wednesday May. 28, 2008)
The FireLink Extended Testbench is transaction based and allows verification level and diagnostic tests to be performed from a system level perspective.
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Virage Logic Speeds Time-to-Market with an All-Digital, High-Performance DDR2/3 PHY+DLL Solution (Wednesday May. 28, 2008)
Supporting speeds of up to 1066 Mbps in 65-nanometer (nm) G processes, the all-digital Intelli DDR2/3 PHY+DLL achieves performance and resolution levels that were previously only possible with analog solutions.
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MIPS Technologies Unveils Silicon-Proven Hi-Fi Audio Playback IP With Lowest Power Consumption Available (Tuesday May. 20, 2008)
The new Audio Codec IP achieves an impressive 100dB dynamic range and -93dB THD while consuming only 7.8mW power when playing back through stereo line outputs at 48kHz.
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Algotronix launches unique DesignTag system for detecting proprietary intellectual property within an operating chip (Monday May. 19, 2008)
DesignTag consists of a small, low power, IP core which is added to the design to be protected and DesignTag reader software and data logging hardware which can sense the tag through the chip package. Each DesignTag IP core has a unique identification code which can be used to look up details of the protected product in a database.
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Evatronix announces its fifth 8051 ISA-based SoC Development Platform - HDLC Connectivity. (Monday May. 19, 2008)
HDLC controller joins other IP cores in the R8051XC-based platform family, Ethernet MAC and USB Controllers, to shorten time-to-market for data communication solutions
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NEC develops Adobe Flash Lite IP (Monday May. 19, 2008)
At Embedded Systems Expo here, NEC System Technology showed an evaluation board featuring what the company claims as the world's first intellectual property (IP) designed to play back content encoded in Adobe Flash Lite.
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Sidense SLP Memory IP Targets Low Power OTP Applications (Tuesday May. 13, 2008)
Sidense today announced the Sidense Low Power (SLP) one-time programmable (OTP) memory macrocells for low-power and cost-sensitive applications that require highly secure information storage.
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Virage Logic Embedded Multi-Time Programmable Non-Volatile Memory Gains Acceptance in Military Applications (Tuesday May. 13, 2008)
NOVeA(R) Memory Features 100K Cycle Programming Endurance, 125 Degrees Celsius Storage Temperature and Minimum of 10-Year Data Retention - Manufactured on a Standard CMOS Logic Process
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Faraday Announces Successful Implementation of 533 MHz ARM(R) Compliant Core -- FA626 in 130nm SoC ASIC (Tuesday May. 13, 2008)
Faraday Technology today announced that it has successfully integrated a hardened 533Mhz ARM(R) compliant core -- FA626 in a complex 130nm SoC ASIC for Radioframe Networks.
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Cosmic Circuits Announces New IP-cores with "Ready for IBM Technology" Validations (Tuesday May. 13, 2008)
Cosmic Circuits Receives IBM Advanced Business Partner Certification and Completes 90nm Silicon Validations in the Power-Management and A/D Converter Space
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TranSwitch announces Industry’s Most Flexible Programmable Silicon Platform for Access Applications (Monday May. 12, 2008)
The first platform, Taurus, which is targeted for access applications, provides programmability, flexibility and cost effectiveness unsurpassed in the market. Taurus includes a targeted set of access interfaces, including GPON, Ethernet, and POTS/TDM.
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ARM Announces PrimeCell Generic Interrupt Controller (Monday May. 12, 2008)
The Generic Interrupt Controller (GIC) is a high-performance, area–optimized PrimeCell peripheral supporting the ARM Generic Interrupt Controller architecture. Highly configurable and programmable, the GIC is suitable for single and multi-processor systems, presenting a common Programmer’s Model accessible via AMBA® 3 AXI™ or AMBA AHB-Lite™ interfaces.
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Dolphin Integration: A Commercial Breakthrough for 'Reduced Cell Stem Libraries' (Monday May. 12, 2008)
Upon launching against all odds, the daring RCSL concept of "Reduced Cell Stem Libraries" for Standard Cells, through a partnership with the Swiss Research Center CSEM, a series of design wins at diverse Fabless customers have proven its worth under the brand name of SESAME.
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Allegro introduces world's first H.264/MPEG-4 AVC High-Profile/High-Definition Hardware Video Encoding IP (Tuesday May. 06, 2008)
Allegro’s H.264 IP core is a real-time hardware encoder targeting mobile phones, camcorders, set-top boxes, webcams and video surveillance applications. Allegro’s IP core can process images up to high-definition resolutions.
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videantis introduces new scalable video solutions up to HD for mobile devices (Wednesday Apr. 30, 2008)
By combining powerful video engines with a programmable stream unit, the v-MP20x0MOB solution packages are capable of encoding and decoding video up to 720p resolution in a wide range of standards on extremely small silicon area without placing load on the host CPU.
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Arasan Chip Systems Announces PCI Express Gen2 End Point Solution (Tuesday Apr. 29, 2008)
Arasan’s PCIe IP core is fully compliant with the PCI-SIG PCIe specification 2.0, increasing throughput to 5 GT/s, while maintaining backward compatibility with Gen 1 systems. Designed to the PIPE specification 1.87, it provides a reliable physical layer interface to industry standard PHYs.
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Altera and HCELL Engineering Announce DO-254-Certifiable Nios II Embedded Processor (Tuesday Apr. 29, 2008)
The embedded processor core complies with the objectives and requirements of the DO-254 hardware avionic standard and meets the highest design-assurance levels. This safety-critical version of the Nios II processor is offered through HCELL Engineering to customers who must comply with DO-254 requirements.
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TranSwitch announces first HDMI 1.3 PHY IP Core operating at 10.5 Gbps (Tuesday Apr. 29, 2008)
The HD-PXL-1.3 transmitter IP core is available in two versions. The first version meets all the current HD (High Definition) standards up to 2.25 Gbps. The second version supports serial communications at a speed of up to 3.5 Gbps per channel for extended HD resolutions, with backward compatibility to the first version of 2.25 Gbps.
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Synopsys Releases Silicon Proven 5.0 Gbps PCI Express 2.0 PHY IP (Monday Apr. 28, 2008)
The DesignWare PHY IP for PCI Express 2.0 includes advanced built-in diagnostic capabilities and ATE test vectors enabling at-speed production testing of the PHY. It is implemented in standard CMOS digital technologies and does not require special process options, providing both ease of integration into a SoC, and ensuring high production yields.
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ASIC Architect Announces the Availability of DDR 3 Controller Cores (Monday Apr. 28, 2008)
The DDR 3 Controller Core supports JEDEC’s DDR 3 DRAM architecture. The DDR 3 Controller core combined with the newly released Multi-Port Intelligent Arbiter and Scheduler (MPIAS) Core provides a winning solution for the high-end ASIC/SoC customers looking for high performance measured by low latency, low power, high throughput, QOS, and fairness control.
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ASIC Architect Announces the Availability of Multi-Port Intelligent Arbiter and Scheduler for DDR Controller Cores (Monday Apr. 28, 2008)
ASIC Architect, Inc. today announced the availability of Multi-Port Intelligent Arbiter and Scheduler (MPIAS) with optional AMBA 3 AXI or AMBA 2 AHB Interface for it successful DDR Controller Cores.
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Dolphin Integration announces a SESAME Library stem for ultra low power and low voltage in 0.18 um (Monday Apr. 28, 2008)
Dolphin Integration's low power and low voltage library SESAME uVSvHS enables operating as low as 0.9 V in 0.18 µm and is available in TSMC G, TSMC ULL and IBM process.