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IP / SOC Products News

• SoC-e networking IP porfolio extends with SpaceWire: The standard for Spacecraft communication networks (Friday Feb. 08, 2019)
  SoCe has released a SpaceWire IP Core is a VHDL core that implements a complete, reliable and fast SpaceWire encoder-decoder with AXI management interface, synthesizable for FPGA and for reconfigurable SoC Devices.
  
  
• Logic Design Solutions Introduces the first member of NVMe HOST RECORDER IPs (Wednesday Feb. 06, 2019)
  The NVME-HOST-RECORDER-ITX-Z7 IP completes an existing family of SATA RECORDER IP of Logic Design Solutions (LDS) in order to provide a complete panoply in embedded recording domain.
  
  
• Xilinx Introduces HDMI 2.1 IP Subsystem (Tuesday Feb. 05, 2019)
  Xilinx today announced that it has introduced a complete HDMI™ 2.1 IP subsystem to its portfolio of intellectual property cores, enabling Xilinx® devices to transmit, receive and process up to 8K (7680 x 4320 pixels) ultra-high-definition (UHD) video in pro AV equipment
  
  
• Mobile Semiconductor Introduces A New 55nm High Density Memory Compiler Especially Designed For IoT Devices (Monday Feb. 04, 2019)
  Mobile Semiconductor announced a new 55nm HD (High Density) memory compiler targeted at the cost sensitive IoT market. The new memory compiler boasts one of the highest density footprints in the industry dramatically reducing the die area and reducing customer product costs for sensors, smart locks, trackers and smart light bulbs.
  
  
• intoPIX and Macnica Preview a 4K AV over 1GbE Module Powered by TICO-XS and ST 2110 IP Transport for Pro AV Market at ISE 2019 (Monday Feb. 04, 2019)
  intoPIX SA, a leading provider of innovative image processing technologies for professional media applications, announced today that it is demonstrating TICO-XS on Macnica’s 4K AV over 1GbE module at ISE 2019.
  
  
• Hardent and Xilinx Collaborate to Deliver Complete 8K Ready DisplayPort 1.4 IP Subsystem (Thursday Jan. 31, 2019)
  Hardent, a leading provider of video compression IP cores and Certified member of the Xilinx Alliance Program, today announced the launch of a new DisplayPort™ 1.4 IP subsystem solution developed in collaboration with Xilinx.
  
  
• Rambus Announces Tapeout of GDDR6 Memory PHY on TSMC 7nm Process Technology (Wednesday Jan. 30, 2019)
  Rambus Inc. today announced the tapeout of its GDDR6 PHY on TSMC 7nm FinFET process technology and is available from Rambus for licensing today.
  
  
• Zhuhai Chuangfeixin Announces Antifuse eFPGA IP (Tuesday Jan. 29, 2019)
  CFX (“Zhuhai Chuangfeixin Technology Co., Ltd.”), a one-stop shop of Flash memory IP and Flash memory chip provider, announced the production release of antifuse eFPGA Bitcell IP.
  
  
• CEVA Locates More Success with Bluetooth 5.1 IP (Tuesday Jan. 29, 2019)
  Supporting the headline new feature of Direction Finding via Angle of Arrival (AoA) and Angle of Departure (AoD) for enhanced location services, the RW-Bluetooth 5.1 IP is available in both Bluetooth Dual Mode and Bluetooth Low Energy flavors.
  
  
• Arasan Announces availability of its Total UFS 3.0 IP Solution for Xilinx FPGA's (Tuesday Jan. 15, 2019)
  
  
  
• New Generation OTP/MTP/NVM from UK Artificial General Intelligence Cosmos IP total solution (Monday Jan. 14, 2019)
  While most of current OTP/MTP solutions are struggled during high temperature and low temperature operations, AGICIP (Artificial General Intelligence Cosmos IP total solution) develops C-Fuse OTP to solve these issues.
  
  
• Toshiba Develops DNN Hardware IP for Image Recognition AI Processor Visconti 5 for Automotive Driver Assistance Systems (Monday Jan. 07, 2019)
  Toshiba today announced the development of Deep Neural Network (DNN) hardware IP that will help to realize advanced driver assistance systems (ADAS) and autonomous driving functions. The company will integrate the DNN hardware IP with conventional image processing technology and start sample shipments of Visconti™5, the next generation of Toshiba’s image-recognition processor, in September 2019.
  
  
• CEVA Introduces WhisPro, Neural Network-Based Speech Recognition Technology For Voice Assistants and IoT devices (Monday Jan. 07, 2019)
  CEVA today introduced WhisPro™, a Neural Network based speech recognition technology targeting the rapidly growing use of voice as a primary human interface for intelligent cloud-based services and edge devices.
  
  
• Innosilicon Announces silicon proven and mass production of the World First Silicon Proven Commercial GDDR6 IP on Samsung's 14LPP Process (Monday Jan. 07, 2019)
  Innosilicon proudly announced silicon successful of world first silicon proven commercial GDDR6 IP on Samsung's 14LPP Process. It is fully compliant to the JEDEC GDDR6 (JESD250) standard, supporting up to 16 Gbps per pin.
  
  
• INVECAS Announces World's First HDMI 2.1 with HDCP2.3 Chip & IP Solutions for TV, AVR, Soundbar and STB (Monday Jan. 07, 2019)
  INVECAS Showcases its Chip & IP Solutions for HDMI 2.1 with HDCP 2.3 at the 2019 International CES in Las Vegas, (Booth #20208 LVCC South Hall 1), Demonstrating the 8K 60Hz Home Theater Experience in Conjunction with Samsung QLED 8K
  
  
• CEVA Announces CEVA-BX, a New All-Purpose Hybrid DSP / Controller Architecture for Digital Signal Processing and Digital Signal Control in IoT devices (Friday Jan. 04, 2019)
  CEVA announced today CEVA-BX, its new all-purpose, hybrid DSP / Controller architecture to address new algorithms of digital signal processing in voice, video, communication, sensing and digital signal control applications.
  
  
• intoPIX introduces the new JPEG XS standard at CES (Friday Jan. 04, 2019)
  intoPIX, leading provider of innovative image processing technologies for professional media applications, is introducing the novel JPEG XS standard with preliminary demonstration of the TICO-XS FPGA and ASIC IP-cores, as well as CPU and GPU SDKs during CES 2019.
  
  
• Arm unveils new image signal processors to meet higher image quality requirements (Thursday Jan. 03, 2019)
  In response to the demand for real-time higher image quality in those devices, today Arm is announcing a new generation of image signal processors (ISPs), the Arm Mali-C52 and Mali-C32 ISPs.
  
  
• SST Announces Automotive Grade 1 Qualification of Embedded SuperFlash Memory on UMC's 55 nm Platform (Thursday Jan. 03, 2019)
  Microchip Technology Inc. (Nasdaq: MCHP) subsidiary Silicon Storage Technology (SST) today announced that its high-speed embedded SuperFlash® technology is qualified to Automotive Electronics Council’s AEC-Q100 Grade 1 on United Microelectronics Corporation’s (NYSE: UMC; TWSE: 2303) 55 nm platform.
  
  
• Arm announces new "Automotive Enhanced" processor designed for safe next-gen driver experiences (Tuesday Dec. 18, 2018)
  Arm introduces latest addition to the Arm Safety Ready program, a new “Automotive Enhanced” processor designed to help enable safe next generation driver experiences
  
  
• Arasan Announces availability of its Total I3C IP Solution for Xilinx FPGA's (Monday Dec. 17, 2018)
  Arasan today announced the immediate availability of its Total MIPI I3C IP Solution for use with Xilinx FPGA’s. The Arasan I3C Master IP and I3C Slave IP have been prototyped on Xilinx FPGA’s and taken to multiple MIPI I3C Interoperability Sessions, including the one recently held as part of MIPI Devcon in Seoul, South Korea.
  
  
• eMemory's Reprogrammable NeoMTP Qualified on GLOBALFOUNDRIES' 130nm BCDLite and BCD Technology Platforms for Automotive Applications (Monday Dec. 17, 2018)
  eMemory today announced that its NeoMTP, Multiple-Times-Programmable embedded non-volatile memory (NVM) IP, has been qualified on GLOBALFOUNDRIES (GF) 130nm BCDLite® and BCD process technology platforms targeting both consumer power management and automotive AEC-Q100 Grade-1 compliant applications.
  
  
• Bluespec, Inc. Releases a Second Family of Open-Source RISC-V Processors to Spur Open Innovation (Monday Dec. 17, 2018)
  Bluespec Inc. has released Flute, its second in a family of commercially supported open-source RISC-V processors. Flute is a configurable 5-stage application processor complementing the previously released 3-stage Piccolo microcontroller, both of which are suitable for IoT.
  
  
• PCS Releases New 3GPP LTE Release 14-Compliant NB-IoT Transceiver IP Supporting High-Band and Low-Band Operation (Friday Dec. 14, 2018)
  Palma Ceia SemiDesign (PCS), a provider of next-generation wireless connectivity solutions, today announced a new transceiver IP supporting LTE NB-IoT Release 14. The transceiver IP is targeted for the Internet of Things (IoT) and Machine-to-Machine (M2M) applications.
  
  
• NSITEXE Develops Test Chip with Next-generation Semiconductor IP Core Called a DFP (Thursday Dec. 13, 2018)
  NSITEXE will unveil a test chip with a next-generation IP core (Data Flow Processor: DFP) that it is developing, as well as a test circuit board to be presented to potential customers and development partners.
  
  
• Minima Processor and NXP Join Forces to Deliver Ultra-Low-Power DSP Solutions (Wednesday Dec. 12, 2018)
  Minima Processor Oy today announced to partner with NXP Semiconductors N.V. (NASDAQ: NXPI) to deliver ultra-low-power digital signal processing (DSP) intellectual property (IP) solutions for a wide range of applications.
  
  
• Faraday Reveals Its Multi-protocol Video Interface IP on UMC 28HPC (Tuesday Dec. 11, 2018)
  Faraday Technology today announced the availability of its multi-protocol video interface IP on UMC 28nm HPC. The Multi-Protocol Video Interface IP solution supports both transmitter (TX) and receiver (RX) featuring a reduced silicon footprint ideal for state-of-the-art panel and sensor interfaces, projectors, MFP, DSC, surveillance, AR and VR, and AI applications.
  
  
• Brite Semiconductor, Naneng Microelectronics, and PLDA Collaborate to Release Complete PCIe 2.0/3.0 Solution (Monday Dec. 10, 2018)
  Brite Semiconductor (“Brite”), a world-leading ASIC design service and DDR controller/PHY IP provider headquartered in Shanghai, China, today announced their collaboration with Naneng Microelectronics and PLDA to deliver a complete PCIe 2.0/3.0 solution based on SMIC’s 40nm and 55nm process technology.
  
  
• Andes Custom Extension Further Accelerates Your High Performance RISC-V Processors (Thursday Dec. 06, 2018)
  Andes Technology today announced its newly-released AndeStar™ V5 CPU cores – N25/N25F, NX25/NX25F, A25 and AX25 – support the Andes Custom Extension™ (ACE) feature. The AndeStar™ V5 architecture is the result of RISC-V technology incorporated with Andes innovations based on rich experience in serving embedded processor IPs for over 10 years.
  
  
• Zeno Demonstrates Scalability of World's Smallest SRAM Bitcell Technology to FinFET Technology Node at IEDM Conference (Thursday Dec. 06, 2018)
  Zeno Semiconductor demonstrated the scalability of its novel 1-transistor/2-transistor Bi-SRAM (bi-stable, intrinsic bipolar) memory technology to FinFET technology node at the IEDM Conference. The results from 14nm and 16nm FinFET technology nodes from multiple foundries follow previous implementation of Bi-SRAM technology in 28nm technology node.