D&R Industry Articles | Most Popular | SoC News Alerts |

IP / SOC Products Articles

• Road to Auto Market Paved With Fault-Tolerant SoCs (Dec. 29, 2014)
  Data protection and redundancy features implemented across entire SoC designs will help teams implement functional safety faster and at a higher quality level
  
  
• SoC clock monitoring issues: Scenarios and root cause analysis (Dec. 19, 2014)
  Clocking and Reset circuitry are the backbone of any SOC. With growing complexity of design, scaling of technology and introduction of multi core architecture, there has been an increase in demand of low power support, resulting in multiple clock and power domains. As this increases the level of complexity in the design, there are chances of introduction of clock domain crossing and reset domain crossing related challenges. As a result, greater are the chances of failures/defects, and any defect in this domain can prove catastrophic, especially when dealing with SOCs for the automotive industry.
  
  
• Moore's Law is Dead: Long Live SoC Designers (Dec. 18, 2014)
  Let’s face it, Moore’s Law has been the free lunch program of the semiconductor industry. And now that Moore’s Law is dead, how will SoC designers continue to survive?
  
  
• ESIstream vs. JESD204B for Ultra-High-Speed Chip-Chip Communications (Dec. 18, 2014)
  The open ESIstream protocol has less encoding overhead and higher data bandwidth than JESD204B. It's also significantly easier to implement ESIstream digital core.
  
  
• FPGA-based FSK/PSK modulation (Dec. 15, 2014)
  This article discusses practical application of a combined Binary FSK and PSK modulator. It highlights how embedded resources can be used to implement an all-digital FSK / PSK modulator, which modulates serial data transmission of a UART (Universal Asynchronous Receiver and Transmitter).
  
  
• USB 3.0 vs USB 2.0: A quick reference summary for the busy engineer (Dec. 15, 2014)
  Abhishek Gupta of Cypress Semiconductor shares the quick reference sheet he created to concisely summarize key differences between USB 2.0 and USB 3.0.
  
  
• USB 3.1: Evolution and Revolution (Dec. 15, 2014)
  USB-IF Worldwide Developers Days introduced developers to the new USB 3.1 specification. On the surface, USB 3.1 seems like it could be only an update to 10G speeds, but this white paper will dig deeper into 10G USB 3.1 to clarify the evolutionary and revolutionary changes in the USB 3.1 specification. USB 3.1 introduces a new 10 Gbps signaling rate in addition to the 5 Gbps signaling rate defined in the USB 3.0 specification.
  
  
• Driving the Future of Automotive Infotainment with Noise Resilient Audio Converters (Dec. 08, 2014)
  This article describes the main automotive application constraints that have an impact on audio performances and thus consumer experience, together with design considerations to be taken care of at silicon Intellectual Property (IP), Systemon- Chips (SoC), application firmware/software and Printed Circuit Board (PCB) levels.
  
  
• A framework for the straightforward integration of a cryptography coprocessor in SoC-based applications (Dec. 01, 2014)
  In this paper, we describe a versatile IP core providing cryptography and security, complemented with a software wrapper including the necessary low-level drivers and communication interfaces between the Linux OS and OpenSSL, the most-widely used cryptographic library in embedded systems. The
  
  
• Slash SoC power consumption in the interconnect (Nov. 25, 2014)
  A modular approach to SoC interconnect slashes power consumption with unit-level clock gating.
  
  
• Effective Optimization of Power Management Architectures through Four standard "Interfaces for the Distribution of Power" (Nov. 24, 2014)
  This article suggests an innovative approach to build an optimal PMNet per application requirements, based on the definition of four standardized voltage levels (further defined as Interfaces for the Distribution of Power). Finally, it demonstrates the advantages of this approach from which regulator suppliers or designers, SoC integrators and system makers can benefit.
  
  
• Real-Time Trace: A Better Way to Debug Embedded Applications (Nov. 24, 2014)
  Firmware and application software development is often the critical path for many embedded designs. Problems that appear in the late phases of the development can be extremely difficult to track down and debug, thus putting project schedules at risk. Traditional debug techniques cannot always help to localize the issue. This white paper shows the benefits of debugging with ‘real-time trace’ hardware assistance, including how it can vastly reduce the amount of time needed to track down problems in the code, and introduces other benefits, such as hot-spot profiling and code coverage, offered by real-time trace systems.
  
  
• Is the Market ready to conquer PCIe 4.0 challenges ? (Nov. 20, 2014)
  PLDA, the company that designs and sells intellectual property (IP) cores and prototyping tools for ASICs and FPGAs, has optimized its ASIC intellectual property (IP) cores for the next generation of the ubiquitous and general purpose PCI Express® I/O specification, 4.0. PLDA’s proven 3.0 architecture enables easy migration to PCIe 4.0, with no interface changes necessary, and preserves existing behavior for seamless integration.
  
  
• A Method to Quickly Assess the Analog Front-End Performance in Communication SoCs (Nov. 17, 2014)
  This white paper outlines a simplified method to determine if the electrical characteristics of any given AFE are adequate for the targeted application such as broadband signal transceivers in the context of wireless or wireline connectivity, cellular communications and digital TV and radio broadcast. Additionally, it illustrates a tool to explore tradeoffs between relative performance and operating modes of different components to find the optimal performance, power, area and cost for SoCs.
  
  
• I-fuse OTP - The OTP of Choice (Nov. 17, 2014)
  OTP stands for “One-Time Programmable”, a device that can only be programmed once to permanently store any kind of information (data for chip IDs, security keys, product feature selection, memory redundancy, device trimming, or MCU code memory). Every chip needs OTPs, as long as they are reliable, available, and affordable.
  
  
• USB battery charging rev. 1.2: Important role of charger detectors (Nov. 06, 2014)
  Other than generous helpings of coffee, what helps industry decrease time to market, drive down cost, and focus more of the design cycle on innovation? Hint: standardization. By defining protocols and operating characteristics, standards have impacted all aspects of technology: device package sizes, pin outs, data and communication interfaces, software drivers, connectors, ESD ratings, environmental compliance, test fixtures.
  
  
• Designing for the Future: The I6400 MIPS CPU Core (Nov. 03, 2014)
  Streaming media, cloud services, wearables, Internet of things (IoT), Software Defined Networks (SDN), Network Function Virtualization (NFV), and Big Data are all relatively new terms in the high-tech industry. However, these terms represent changes in the way data is collected, transmitted, and processed. In addition, the cumulative effect of the impact of the technology behind these terms represents an increasing rate of change and challenges designing solutions to keep pace.
  
  
• Achieving 200-400GE network buffer speeds with a serial-memory coprocessor architecture (Oct. 27, 2014)
  In this Product How-To, Michael Miller of MoSys describes the challenges faced on the wired Internet backbone as increased network line and packet rates cause throughput bottlenecks at the processor/external DDR memory interface. He then shows how a new serial chip-to-chip protocol the company has developed, called the GigaChip Interface (GCI), with 200-400 GE data rates and 4.5 B read/write transactions, can be used to eliminate such bottle necks.
  
  
• Choosing the right A/D converter architecture and IP to meet the latest high speed wireless standards (Oct. 15, 2014)
  Internet enabled mobile devices are continuing to become more prevalent in the modern world. With this proliferation of smart, connected devices – many of which are battery powered – comes a greater need for power efficient wireless transceivers. In addition to meeting stringent power specifications, RF system designers must also ensure that their devices adhere to the latest wireless standards, including Long Term Evolution (LTE) and Wi-Fi.
  
  
• Performance analysis of 8-bit pipelined Asynchronous Processor core (Oct. 13, 2014)
  In this paper, power, area performance parameters of 8-bit pipelined asynchronous processor is measured and compared over similar feature synchronous processor. The Asynchronous processor supports 28 Arithmetic and Logical Instructions.
  
  
• Rethinking the FFT (Oct. 06, 2014)
  It is well known that the discrete Fourier transform (DFT) is of central importance to many signal processing applications, in particular high data-rate multicarrier applications such as wireless communications, which is the second largest market for semiconductor chips. Here a DFT is required in a large variety of wireless transmission protocols that are based on some form of orthogonal frequency division multiplexing (OFDM).
  
  
• Understanding layers in the JESD204B specification: A high speed ADC perspective, Part 2 (Oct. 02, 2014)
  We continue with the second and final part of this article. Part 1 discussed an Introduction and Data Flow through the layers of the JESD204B interface, as well as the Application and Transport layers discussed in depth. Part 2 will continue with a thorough discussion of Data Link layer as well as the Physical Link layers.
  
  
• Market conditions swing in favor of the custom SoC (Oct. 01, 2014)
  The system-on-chip (SoC) is now a part of almost all electronic systems. As an integrated circuit (IC) that pulls together microprocessor cores, systems logic, and I/O functions, the SoC enables a wide range of product designs and is driving new markets such as the Internet of Things (IoT) and the cyber-physical systems that now underpin many industrial and automotive applications.
  
  
• Targeting SoC address decoder faults using functional patterns (Sep. 29, 2014)
  Even though you have thoroughly verified your SoC design during the development cycle, sometimes critical faults during manufacturing can lead to failure in the field, one of the most serious of which is the address decoder stuck-at fault. This is a critical fault that must be tested for on each and every piece of silicon that needs to pass qualification for an industry standard.
  
  
• Improve FPGA communications interface clock jitters with external PLLs (Sep. 29, 2014)
  In this Product-How-To article, IDT’s Fred Hirning describes the problems faced in dealing with clock jitter in FPGA-based high-speed communications interfaces such as SerDes and how external phase locked loops (PLLs) such as the company’s VersaClock5 and FemtoClock NG clock generator can be used to resolve them.
  
  
• Understanding layers in the JESD204B specification: A high speed ADC perspective, Part 1 (Sep. 25, 2014)
  In this two-part article, the author will help designers understand how high speed ADCs can properly use and understand how to use to your design advantage the JESD204B standard for the ADC to FPGA interface. Part 1 will discuss an Introduction and Data Flow through the layers of the JESD204B interface, as well as the Application and Transport layers discussed in depth.
  
  
• Product how-to: Reliable SoC bus architecture improves performance (Sep. 24, 2014)
  This paper describes a modeling project to architect the bus topology and evaluate the read/write traffic patterns for a new multimedia System-On-Chip. Using the selected modeling and simulation exercise, we were able to validate the entire architecture in three months. In the process, we learned about architecture behavior and were able to test a large number of operating scenarios to achieve optimum performance in minimal time.
  
  
• RISC-VLIW IP Core for the Airborn Navigation Functional Oriented Processor (Sep. 22, 2014)
  Development of miniature high performance data processing systems needs combined optimization of algorithms and processor architecture. Today's microelectronics allows designing almost all the computer architectures as SoC. The paper is devoted to the practical realization of SINS algorithms by means of SoC.
  
  
• Low-loss compression of CPRI baseband data (Sep. 19, 2014)
  This paper describes a method of using Mu-Law compression for Gaussian-like waveforms – for example, baseband IQ data, as used in CPRI interfaces.
  
  
• Reducing Power Consumption while increasing SoC Performance (Sep. 15, 2014)
  Designers of today's high-performance multi-client SoCs struggle to achieve the best possible performance/watt for their designs. Every generation of product must improve the customer's user experience by delivering more performance. While at the same time battery life must increase with each subsequent product generation.