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IP / SOC Products News

• Arteris Enhances Network-on-Chip Offerings to Address Full Range Of SoC Designs (Monday Nov. 09, 2009)
  Arteris today announced the availability of two new on-chip interconnect products, the FlexNoC and FlexWay packages. With these offerings, Arteris expands the capabilities of its market-leading NoC Solution to address the complete range of SoC design styles, sizes and complexities.
  
  
• Dolphin Integration launches a new breed of cache controller, dynamically self-configured to minimize power consumption (Friday Nov. 06, 2009)
  Traditional cache controllers are offered to improve the system frequency, involving a CPU and its program memory. But these caches are not concerned with power consumption. As a consequence, these solutions do not fit applications targeting low power. To bridge this gap, Dolphin Integration offers a new breed of cache controller: I-Stratus-LP.
  
  
• ASICS World Services Announces USB 3.0 Device IP Core (Tuesday Nov. 03, 2009)
  ASICS World Services, LTD. today released it's USB 3.0 Device IP Core. The USB 3.0 Device IP Core, supports SuperSpeed transfer speeds of 5Gbit/sec., and can be implemented in any technology, from FPGA to full custom ICs. Direct support is provided for Xilinx Virtex 5 FPGA with GTX transceiver, offering a true single chip solution, without the need for external PHYs. This IP Core also features an industry standard PIPE PHY interface for integration with 3rd party PHYs.
  
  
• HDL Design House Announces I2S Soft IP Core (Tuesday Nov. 03, 2009)
  HDL Design House has announced I2S soft IP core (HIP 3700). HIP 3700 I2S soft IP core is based on a generic, highly modular architecture from which a variety of solutions can be easily created to effectively and efficiently address customers’ specific requirements.
  
  
• Arasan Chip Systems Announces CompactFlash 4.1 Controller Family (Tuesday Nov. 03, 2009)
  Arasan announced the availability of CompactFlash/CF+ IP Host and Device cores that are compliant with CF+ and CompactFlash(R) Specification Revision 4.1.
  
  
• Noesis Technologies releases ITU G.704 E1 Framer/Deframer IP core (Tuesday Nov. 03, 2009)
  Noesis Technologies announced today the immediate availability of its ITU G.704 compliant E1 Framer/Deframer IP core (ntE1_G704).The IP core is designed for E1 networks and is compliant with ITU recommendations G.704, G.706, G.732, G.775 and O.163.
  
  
• MIPS Technologies Introduces New Processor Cores with 32-bit Performance and near 16-bit Code Size (Monday Nov. 02, 2009)
  MIPS today introduced a new core family providing the highest levels of system performance for extremely cost-sensitive embedded applications such as 32-bit microcontrollers (MCUs), home entertainment, personal entertainment and home networking. The new MIPS32® M14K and M14Kc cores are the first MIPS32-compatible cores that also execute the new microMIPS instruction set architecture (ISA), achieving high performance of 1.5 DMIPS/MHz with an advanced level of code compression.
  
  
• MoSys Announces Availability of 40nm PCI Express 2.0 PHY (Monday Nov. 02, 2009)
  MoSys today announced the availability of its PCI Express 2.0 PHY. MoSys' PHY complies with the PIPE 2.0 specification and provides the physical layer (PHY) interface that connects to industry standard PCI Express 2.0 controllers.
  
  
• Dolphin Integration introduces Orion, the densest ROM (Monday Nov. 02, 2009)
  Orion is the latest ROM architecture conceived by Dolphin Integration. Benefiting from the “Two in one” Patent for high density, the metal-programmable ROM Orion enables SoC designers to get an impressive decrease of fabrication costs. The Orion architecture is already available for the TSMC 90 nm LP process.
  
  
• New Tensilica DPU Family Delivers 10 GigaMAC/sec DSP Performance, Tops 1 GHz Mark (Monday Nov. 02, 2009)
  Tensilica today introduced the Xtensa LX3 high-performance dataplane processor (DPU) core optimized for digital signal processing (DSP) and control in the system-on-chip (SOC) dataplane.
  
  
• Synopsys Unveils 30 Percent Smaller Area, Low Power USB 2.0 PHY IP for 28-nm Processes (Thursday Oct. 29, 2009)
  Connectivity IP Leader Continues to Innovate with the DesignWare USB 2.0 picoPHY - The First PHY IP to Support USB 2.0 Battery Charging v1.1 and OTG 2.0 Specifications
  
  
• Sital Announces the release of Mil-Std-1553 IP core with PCI interface (Wednesday Oct. 28, 2009)
  Sital Technology is expanding its IP products base with the release of the new Mil-Std-1553 IP Core with the addition of PCI interface.
  
  
• Synopsys Announces 40th DesignWare Audio Codec IP (Wednesday Oct. 28, 2009)
  Synopsys today announced the availability of its 40th audio codec IP with the release of the DesignWare 96 dB Hi-Fi Audio IP in the SMIC 65-nanometer (nm) process.
  
  
• Arasan Chip Systems First to Announce SDIO 3.0 Device Controller IP (Tuesday Oct. 27, 2009)
  Arasan announced today the availability of the world's first Secure Digital IO (SDIO) 3.0 Device Controller IP compliant with the latest SDIO Specification v3.0.
  
  
• Dolphin Integration launches Linear Regulators at 65 nm for Ultra Low-Noise (Monday Oct. 26, 2009)
  Dolphin Integration continues its strategy with Inductorless converters and announces today the availability of its latest Low Drop Out Linear Regulator at 65 nm.
  
  
• Jointwave Announces Green H.264 HD Encoder IP (Monday Oct. 26, 2009)
  Jointwave announces its new E2, E3, and E3 series of H.264 HD Video Encoder ASIC IP, which targets super low power consumption products for mobile and embedded applications.
  
  
• Rambus Achieves Power Efficiency Breakthrough for Mobile Memory Solutions (Wednesday Oct. 21, 2009)
  Rambus today announced it has achieved a new breakthrough level of power efficiency with its latest silicon test vehicle developed through its Mobile Memory Initiative (MMI). The latest silicon-validated results demonstrate that through the use of MMI innovations, a high-bandwidth mobile memory controller can achieve a world-leading power efficiency of 2.2mW/Gbps.
  
  
• ARM Unveils New AMBA System IP For Low Power and Media Rich SoC Designs (Wednesday Oct. 21, 2009)
  ARM today announced the launch of new system IP products from the ARM® AMBA® family: the AMBA Network Interconnect with Advanced Quality of Service, a new Dynamic Memory Controller, and the Verification and Performance Exploration tool.
  
  
• ARM Delivers The Internet Everywhere With Most Power-Efficient and Cost-Effective Multicore Processor (Wednesday Oct. 21, 2009)
  ARM today announces the launch of the ARM® Cortex™-A5 MPCore™ processor, the smallest, lowest power ARM multicore processor capable of delivering the Internet to the widest possible range of devices, from ultra low cost handsets, feature phones and smart mobile devices, to pervasive embedded, consumer and industrial devices.
  
  
• Tensilica Introduces Small, Ultra-Low Power Dataplane Processor Core for Deeply Embedded Control (Monday Oct. 19, 2009)
  Tensilica today introduced the Xtensa 8 customizable processor, the eighth generation of its market leading low-power dataplane processor cores (DPUs). The Xtensa 8 processor core starts at a size of just 15,000 gates, consuming less than 0.05mm2 in 40nm process technology - making it one of the smallest licensable controller cores on the market.
  
  
• Jointwave presents H.264 solution for FPGA/ASIC (Monday Oct. 19, 2009)
  Jointwave LLC, a leading provider of video codec IP, presented its H.264 series encoder in HYSTA 2009 Annual Conference
  
  
• Arasan First to release SD3.0 Family of Host Controller IPs (Thursday Oct. 15, 2009)
  Arasan formally announced today the availability of the world's first, proven, Secure Digital eXtended Capacity (SDXC) / SDIO 3.0 / eMMC 4.4 Host Controller IP. This IP is compliant with the latest SD Physical Layer Specification v3.0, Part E1 SDIO 3.0 specification and JEDEC's eMMC 4.4 specification. SoC designers now have the flexibility to tailor their memory subsystem to the functional requirements of their platforms.
  
  
• Tensilica's HiFi Audio DSP First IP Core to Achieve DTS-HD Master Audio Logo Certification (Tuesday Oct. 13, 2009)
  Tensilica, Inc. announced today that it has been granted DTS-HD Master Audio logo certification for the HiFi Audio DSP (digital signal processor). This makes Tensilica's HiFi Audio DSP the first IP (intellectual property) core to achieve certification.
  
  
• Silicon Image Introduces New 18 Megapixel Camera Processor IP Core (Monday Oct. 12, 2009)
  Silicon Image today introduced the camerIC-18, the newest member of its family of camerIC camera processor IP cores. With its high-quality 18 megapixel (MP) image signal processing (ISP) technology, the camerIC-18 is targeted for integration into digital still camera (DSC) and video System-on-a-Chip (SoC) application processors for mobile devices such as cell phones, portable multimedia players (PMPs) and netbooks.
  
  
• Xelic Announces Availability of Two New Cores in support of ITU G.Sup43 for Optical Transport Network (OTN) Applications (Monday Oct. 12, 2009)
  Xelic today announced the availability of their new 10G Multiprotocol Mapper Core (XCO2M) along with a PCS to XGMII Encoder/Decoder Core (XCI2PX) for OTN applications. These two cores are the latest in Xelic's growing portfolio of cores for OTN Applications.
  
  
• On2 Technologies Releases Hantro 9190 Multiformat Hardware Decoder with On2 VP6 Support (Thursday Oct. 08, 2009)
  On2 today announced that it has released its new flagship hardware video decoder design, the Hantro(TM) 9190. The 9190 design supports video playback up to full HD (1080p) resolution at 60 frames per second (fps) in multiple formats including On2 VP6 for Adobe Flash Player and Sun JavaFX, DivX 3, 4, 5, 6, H.264, H.263, Sorenson Spark, MPEG-1, MPEG-2, MPEG-4, VC-1/WMV9 and RealVideo 8, 9 & 10, as well as up to 66 megapixel JPEG still images.
  
  
• ARM Announces 45nm SOI Test Chip Results That Demonstrate Potential 40 Percent Power Savings Over Bulk Process (Thursday Oct. 08, 2009)
  ARM announced the results from a silicon-on-insulator (SOI) 45nm test chip that demonstrate potential power savings of up to 40 percent over traditional bulk process for manufacturing chips. The test chip was based on an ARM 1176™ processor and enables a direct comparison between SOI and bulk microprocessor implementations.
  
  
• IMEC's multi-threaded ADRES processor architecture ready for licensing (Tuesday Oct. 06, 2009)
  Today, IMEC unveils the second generation of its ADRES processor architecture (architecture for dynamically reconfigurable embedded systems). ADRES now supports multithreading, and has doubled its performance and energy efficiency compared to the first ADRES generation. This positions ADRES as a building block for future 4G devices. ADRES can be licensed from IMEC and is targeted at chip manufacturers.
  
  
• Dolphin Integration paves the way to the "Super-ViC" generation for audio applications (Friday Oct. 02, 2009)
  Dolphin Integration today is paving the way to a new generation of Virtual Components starting with loDAC95-SV01, the first audio DAC empowered with its own oscillator and embedded voltage regulator.
  
  
• Arasan Chip Systems First to Release MIPI D-PHY Compliant with the version 1.0 Specification (Wednesday Sep. 30, 2009)
  Arasan announced the availability of the MIPI® D-PHY IP compliant with the v1.0 standard released September 22, 2009 by the MIPI Alliance. With this release, Arasan continues to demonstrate its commitment to its Strategic Mobile Initiative by being the first to deliver fully verified MIPI IP comprising of software stacks, controllers and the D-PHY.