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IP / SOC Products News

• Moortec Announces SPI Block (MR74040) for Low Power Applications (Tuesday Sep. 29, 2009)
  Moortec Announces SPI Block (MR74040) for Low Power Applications. The MR74040 is a synchronous serial-data interface adhering to the SPI protocol of communications.
  
  
• Virage Logic Expands SiPro(TM) Product Portfolio with New Production-Proven Advanced Interface IP Offerings (Tuesday Sep. 29, 2009)
  Virage today announced new additions to its recently introduced SiPro(TM) product line of production-proven advanced interface IP. The expanded product line now includes complete standards-based solutions for PCI Express (PCIe) and Mobile Industry Processor Interface (MIPI(R)) as well as a unique multi-protocol IP solution for High-Definition Multimedia Interface (HDMI), Digital Visual Interface (DVI) and DisplayPort interfaces. The Virage Logic SiPro product portfolio is the result of a collaboration with AMD (NYSE: AMD) that was announced in January 2009.
  
  
• Evatronix Introduces the World's Fastest SD/SDIO/MMC Host Controller (Wednesday Sep. 23, 2009)
  Evatronix today announced its SDIO-HOST controller has been updated to meet the latest specifications and now supports SD 3.0, SDIO 2.0 and MMC/eMMC 4.4 standards. These specifications allow support of SDXC cards, which go beyond the 32 GB limit of SDHC products and sets the capacity bar at 2 TB of data.
  
  
• eMemory Breaks New Ground in Launching Its Industrial Grade Embedded NVM for Power Management Solution (Wednesday Sep. 23, 2009)
  eMemory today announces its Neobit OTP memory has reached higher temperature stability up to maximum 125℃ for minimum 10 years data retention (125℃/10yrs). The 125℃/10yrs Neobit is the first logic OTP memory solution that has passed 0.35um BCD process qualification and entered into commerce in volume production in TSMC.
  
  
• Dolphin Integration Library portfolio at 65 nm (Monday Sep. 21, 2009)
  Dolphin Integration focuses on providing users with a full offering featuring embedded memories and standard cells of diverse optimizations for the 65 nm process node.
  
  
• Rambus and Kingston Co-Develop Threaded Module Prototype for Multi-Core Computing (Thursday Sep. 17, 2009)
  Rambus and Kingston Technology today announced a collaborative development of a threaded module prototype using DDR3 DRAM technology. Initial silicon results show an improvement in data throughput of up to 50 percent, while reducing power consumption by 20 percent compared to conventional modules.
  
  
• Faraday SATA 3G PHY & controller First to Achieve Compliance in UMC's 90nm Process Technology (Thursday Sep. 17, 2009)
  Faraday Technology today announced that their SATA 3G solution is the first to pass SATA-IO compliance test in UMC's 90 nanometer process technology, and becomes the 2nd IP provider in the world to have IP in SATA-IO's Building Block Listing.
  
  
• Cycleo unveils its first innovative semiconductor IP bringing unprecedented range to wireless data transmission (Thursday Sep. 17, 2009)
  Cycleo today announces Lora™, an innovative semiconductor IP bringing unprecedented range to wireless data transmission. Based upon a disruptive patented technology, Lora (as Long Range) allows robust long range wireless communications at very low power.
  
  
• ARM Announces 2GHz Capable Cortex-A9 Dual Core Processor Implementation (Wednesday Sep. 16, 2009)
  ARM announced today the development of two Cortex™-A9 MPCore™ hard macro implementations for the TSMC 40nm-G process, enabling silicon manufacturers to have a rapid and low-risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2GHz.
  
  
• Arasan Chip Systems adds IEEE 1588 PTP support to Ethernet IP Core (Wednesday Sep. 16, 2009)
  Arasan announced that it has expanded its Ethernet Portfolio by integrating hardware support for IEEE 1588 Precision Time Protocol (PTP). Mission critical environments such as factory automation systems, networking environments, manufacturing, test and measurement systems rely on IEEE 1588 to maintain precise timing synchronization in order to execute activities in real-time.
  
  
• Microtronix Boosts Performance of MDDR Memory Controller IP Core to 200 MHz (Wednesday Sep. 16, 2009)
  Microtronix today announced an upgrade of their Multi-port MDDR Memory Controller IP Core to support 200 MHz Mobile DDR (MDDR) memory devices. This upgrade represents an approximate 20% boost in system performance from the previous version.
  
  
• Element CXI Announces nGEN Elemental Computing Array, a Fully Reconfigurable Platform for 4G Networks (Monday Sep. 14, 2009)
  Element CXI today introduced its new nGEN Elemental Computing Array (ECA) platform at 4G World in Chicago. The nGEN ECA offers OEMs a common platform for end-to-end, software defined solutions from baseband to front-end processing.
  
  
• Radiocomp releases 4G Ready OBSAI RP3 v4.1 IP core for LTE, WCDMA and WIMAX (Wednesday Sep. 09, 2009)
  Radiocomp's OBSAI RP3 v4.1 IP core comes ready with a fully-flexible and multi-standard IQ mapping module with embedded Ethernet MAC functionality, thereby minimizing engineering efforts and time to market for standards-based radio access products for LTE, GSM, WCDMA, CDMA and WIMAX.
  
  
• Synopsys First to Announce DDR3 IP with Support for 2133 Mbps Data Rates and 1.35V DDR3L (Wednesday Sep. 09, 2009)
  Synopsys today announced that its DesignWare® DDR3/2 PHY and digital controller IP supports the emerging 1866 and 2133 Megabits per second (Mbps) data rates currently being added to the JEDEC DDR3 standard.
  
  
• Barco delivers its JPEG 2000 IP cores on all 40nm FPGA platforms (Monday Sep. 07, 2009)
  Barco Silex, Barco's center of competence for embedded video coding electronic and design services, announces the support of its JPEG 2000 IP cores on all high-performance and low-cost 40nm FPGA families.
  
  
• SiliconGate Introduces 50 nA Crystal Oscillator for 0.35um to 40-nm Process Technologies (Wednesday Sep. 02, 2009)
  SiliconGate's Nano Power Crystal Oscillators are fully integrated and require no external capacitors or references. The IP is made available in leading process technologies from 0.35-μm down to 40-nm, and includes behavioral models for system development.
  
  
• Altera's RapidIO IP Core Passes RIOLAB Device Interoperability Testing (Tuesday Sep. 01, 2009)
  Altera today announced its RapidIO® MegaCore function, version 9.0, successfully passed RIOLAB's Device Interoperability Level-3 (DIL-3) testing. Altera is the first FPGA vendor to offer a Serial RapidIO intellectual property (IP) core that is fully qualified by RIOLAB.
  
  
• Dolphin Integration announces a benchmarking solution for fair comparison of the in-SoC performances of embedded memories (Monday Aug. 31, 2009)
  With the objective to avoid any illusion about density, Dolphin Integration proposes a virtual component of IP, named LOGOS, as an alternative to the traditional memory evaluation process based on compiler outputs.
  
  
• iWave announces the Host controller for SDXC card which is compatible with the SD Physical Layer specification V3.0 (Monday Aug. 31, 2009)
  iWave announces the Host controller for SDXC which is compatible with the SD Physical Layer specification V3.0.The core developed, supports 32 bit AHB LITE Host interface working at SOC interface frequency and is compatible with the standard register set for the host controller as per SD host controller specification Version2.0.
  
  
• Arasan Chip Systems adds MIPI HSI IP to its Strategic Mobile Initiative Program (Wednesday Aug. 26, 2009)
  Arasan announced the release of its MIPI® High Speed Synchronous Interface (HSI) Controller IP and Software Stack. The HSI Controller IP and Software Stack are compliant with the HSI v1.0 specification.
  
  
• Rapid Bridge Introduces LiquidCell Library to Bring Unparalleled Flexibility to Chip Design at 40 Nanometer Process Node (Wednesday Aug. 26, 2009)
  Rapid Bridge announced today that its revolutionary LiquidCell™ library is now available at 40nm process node. LiquidCell consists of a metal-programmable sea of transistors that can be configured into millions of usable elements from a library of over 700 standard cells.
  
  
• Tensilica's ConnX D2 DSP Engine Combines Outstanding Performance, Compact Size, and Easy Programmability (Monday Aug. 24, 2009)
  Tensilica today introduced the high-performance, small, low-power ConnX D2 16-bit dual-MAC (Multiply Accumulator) DSP (Digital Signal Processor) engine for its proven Xtensa LX dataplane processor cores for SOC (System-on-Chip) designs. The ConnX D2 DSP engine provides uncompromised performance from C code, unlike many other DSPs that require time consuming assembly coding for maximum performance.
  
  
• intoPIX introduces optimized Spartan-6/Virtex-6 JPEG 2000 encoders & decoders range focusing on Low Power and Ultra High Resolution (Monday Aug. 24, 2009)
  intoPIX announces the company’s migrating solution for Xilinx® Spartan-6 & Virtex-6 FPGA platforms. With this release, intoPIX enables its customers with a new range of JPEG 2000 IP-Cores, allowing them to significantly reduce their Bill of Materials while giving access to higher performances.
  
  
• Elliptic Curve CryptoProcessor Core from Athena Set New Standard for NIST P-Curve Performance (Wednesday Aug. 19, 2009)
  The Athena Group today announced the industry's fastest elliptic curve accelerator core. With an incredibly small area footprint, starting at less than 200K-gates, the E5200 is both the highest performance core available and the highest density in terms of performance per unit area.
  
  
• Arasan Chip Systems Announces SDXC Card Controller IP (Wednesday Aug. 19, 2009)
  Arasan announced today the availability of the World’s first Secure Digital eXtended Capacity (SDXC) Card Controller IP compliant with the latest SD Memory Specification v3.0. Arasan’s SDXC Card Controller supports Ultra-High Speed I (UHS-I) operation and incorporates all standard security features.
  
  
• Faraday Offers 55nm/ 65nm miniIO with around 40% Area-Saving and Robust ESD Performance (Tuesday Aug. 18, 2009)
  Faraday Technology Corporation (TAIEX: 3035) today announced the availability of its innovative miniIO™ at 55nm and 65nm. Compared with general IO pads, Faraday's miniIO™ reduces the chip area by up to 40% for a pad-limited design with 500 pins, while keeping the same programming IO functionality, and achieving robust ESD performance.
  
  
• Synopsys Delivers Comprehensive HDMI IP Solution for 90-nm to 40-nm Process Technologies (Thursday Aug. 13, 2009)
  Synopsys' DesignWare® IP for the HDMI interface is compliant to the standard specification and supports High-bandwidth Digital Content Protection (HDCP). Synopsys also provides a roadmap for HDMI 1.4 with product availability anticipated at the end of 2009.
  
  
• Micron Validates Denali's NAND Controllers for High-Performance Applications (Monday Aug. 10, 2009)
  Denali today announced that Micron Technology has validated Denali's Databahn NAND Flash controller IP and FlashPoint products with its line of ONFI 2-based flash devices.
  
  
• Evatronix Fastest 8051 Microcontroller Now Fully Supported by ARM Keil uVision4 IDE (Monday Aug. 10, 2009)
  Evatronix SA, today announced the full support of its R8051XC2 microcontroller IP, the world’s fastest 8051 compatible design, by the ARM® Keil™ μVision4 Integrated Development Environment.
  
  
• Perceptia confirms performance of 11-GHz 0.4-ps 40-nm DSP-based PLL hard IP Core (Thursday Aug. 06, 2009)
  Perceptia today confirmed functionality and ultra-high performance of its DeepSub™ pPLL01 hard IP core. The pPLL01 has an output frequency ranges from 9 to 11-GHz and can be driven from sources down to 20-MHz.