D&R Headline News | Most Popular | SoC News Alerts | |

IP / SOC Products News

• Altera Ships Industry's First FPGA-based Audio/Video Development Kit Supporting Triple Rate SDI (Tuesday Sep. 05, 2006)
  Altera to Showcase New Development Platform at IBC2006
  
  
• Intelop announces industry's first customizable TCP-Offload Engine at 2-Gpbs with integrated Ethernet MAC Silicon IP for SOC, ASIC and FPGA customers in Network equipment, Network Security, Telecom, SAN/NAS markets (Monday Sep. 04, 2006)
  Integrated TOE+2G bit Ethernet MAC silicon IP with security features provides enhanced functionality in Layer-2-7 Switches/Routers, IPS/IDS appliances and Network Security appliances. Advanced architecture with built in scalability allows customers to tar
  
  
• Kenwood, Fraunhofer IIS, and STMicroelectronics Demonstrate Prototype of a Digital Radio Mondiale(TM) Receiver (Monday Sep. 04, 2006)
  Fully Working Prototype of a DRM(TM) Receiver to be Featured at the Kenwood and Fraunhofer Booth, September 1-6, at IFA 2006, in Berlin
  
  
• Microtronix Launches High Performance Multi-port SDRAM Memory Controller IP Core (Wednesday Aug. 30, 2006)
  Boosts memory performance by more than 6 times over other standard memory controller IP Cores.
  
  
• Faraday Technology Offers Improv Systems' Pre-Configured Application Processor Cores (Wednesday Aug. 30, 2006)
  Improv's popular cores for DSP, media and voice applications available as part of Faraday's custom chip offering
  
  
• Renesas Technology Develops Hardware IP Supporting Video Compression Standard VC-1 Decode Function (Monday Aug. 28, 2006)
  Decoding of MPEG-4, H.264, and VC-1 compatible video content possible with one IP
  
  
• Silterra and eMemory Offer CMOS Logic-Based OTP Memories (Thursday Aug. 24, 2006)
  Silterra Malaysia Sdn. Bhd. and eMemory Technology today announced that the companies have verified the Neobit™ one-time-programmable (OTP) memory on Silterra’s 0.18-micron CL180G and CL180H CMOS process technologies.
  
  
• TaraCom announces GPON SerDes IP PHY in 90 nm process (Tuesday Aug. 22, 2006)
  TaraCom has ported the Serial ATA (SATA) core intellectual core property (IP) for integration into SoC and ASIC design.
  
  
• Digital Blocks Delivers the DB1800 NTSC / PAL / SECAM Video Sync Separator IP Core (Wednesday Aug. 16, 2006)
  The DB1800 accepts a NTSC/PAL/SECAM composite video signal, auto-detects the standard, and outputs the horizontal sync, vertical sync, chroma burst blanking, and field 1 or 2 (odd or even) detection
  
  
• Altera, Sarance Technologies and Cortina Systems Join Forces on First Interlaken Protocol IP Core for FPGAs (Monday Aug. 14, 2006)
  The Interlaken protocol IP core, created by Sarance Technologies, lets communication and storage network equipment developers apply the new interconnect specification using Altera® Stratix® II GX FPGAs.
  
  
• videantis announces 65nm silicon for v-MP2000 family (Monday Aug. 14, 2006)
  videantis GmbH, a leading IP provider of multi-standard video processing solutions, announces the availability of silicon samples of its v-MP2000 video processor family manufactured in the most advanced 65nm technology
  
  
• Improv Systems Offers Pre-Configured Application Processor Cores Based On Its Popular High Performance, Low Power Jazz Platform (Monday Aug. 14, 2006)
  The cores come in three families: Jazz DSP™ for general-purpose DSP processing, Jazz Media™, for multimedia processing and Jazz Voice™ for Voice-over-IP
  
  
• Lattice Announces Low Cost Programmable SPI-4.2 Solution for LatticeECP2 FPGAs (Monday Aug. 07, 2006)
  Lattice's SPI-4.2 solution is supported by Lattice’s new IPexpress™ FPGA design tool module
  
  
• Rambus Releases Mass Production Specification for XDR Clock Generator (Monday Aug. 07, 2006)
  XCG Supports High-Volume Production Infrastructure for XDR Memory Solutions
  
  
• Faraday Adds New Memory Compilers to its miniIP Platform; 70% AC Power Saving and 13% Area Saving without Performance Penalty (Monday Aug. 07, 2006)
  The new ultra-low-power single-port SRAM compiler (miniRAM™) and ROM compiler (miniViaROM™) achieve more than 70% AC power saving and 13% die size saving without any performance losses
  
  
• PLDA Collaborates with National Instruments to Unveil the Industry's First FPGA-Based PXI Express Development Kit (Friday Aug. 04, 2006)
  The x1 Endpoint add-in board, based on Altera's Cyclone II FPGA, is a complete production-ready or system prototyping solution.
  
  
• Global Unichip Introduces H.264 Total Solution Verified on GPrime Platform (Thursday Aug. 03, 2006)
  This solution has been fully verified on GUC’s GPrime/UMVP-2000 AMBA-based Platform, which is composed of H.264 synthesizable RTL cores, AHB wrapper, video output module, and AV-Sync. GUC’s H.264 total solution aims to facilitate customers’ SoC designs on
  
  
• MoSys Launches 65nm Macro Program (Wednesday Aug. 02, 2006)
  Signs First 65nm Technology Licensing Agreement with Major IDM and Initiates CLASSIC Macro Designs with Pure-Play Foundries
  
  
• Details of ST's Nomadik processor disclosed (Thursday Jul. 27, 2006)
  An STMicroelectronics executive provided a glimpse of its future Nomadik multimedia processor platform consisting of multiple CPUs, DSPs and subsystems on a single chip
  
  
• LogicVision and GDA Technologies Partner to Deliver LogicVision's Unique High Speed I/O Test IP (Wednesday Jul. 26, 2006)
  LogicVision and GDA Technologies, Inc today announced an alliance to deliver design services for high speed I/O test with LogicVision’s comprehensive at-speed test IP for high speed serializer/deserializer (SerDes) circuits
  
  
• Iran develops 32-bit processor (Wednesday Jul. 26, 2006)
  Iran has designed and produced a 32-bit microprocessor for the first time, according to the Fars News Agency based in Tehran.
  
  
• Avery Design and ASIC Architect Team to Deliver Serial ATA (SATA) IP Solution (Tuesday Jul. 25, 2006)
  Avery Design Systems and ASIC Architect today announced a cooperative effort to deliver a comprehensive Serial ATA (SATA) design and verification IP solution
  
  
• eMemory Technology Inc. announces the launch of Neobit one-time programmable (OTP) IP on 0.15-micron high voltage process (Monday Jul. 24, 2006)
  eMemory, the leading provider of embedded non-volatile memory IP, extends comprehensive Neobit solutions in high voltage process covering 0.6-micron, 0.5-micron, 0.35-micron, 0.25-micron, 0.22-micron, 0.18-micron and 0.15-micron, which are slated to be si
  
  
• Lattice FPGA IP Support Expands With Multimedia Cores From Art of Silicon (Monday Jul. 24, 2006)
  Art of Silicon Optimizes JPEG IP Cores for the LatticeECP2, LatticeSC & LatticeXP FPGA Devices
  
  
• Virage Logic and MIPS Technologies Introduce New Core-Optimized IP Kits for MIPS32(R) 24K(R), 24KE(TM) and 34K(TM) Core Families in 90nm G Process (Monday Jul. 24, 2006)
  New Kits Enable 24K and 24KE Processor Cores to Achieve Clock Frequencies of Up to 660 MHz
  
  
• ARM Announces AMBA 3 AXI Design Tools And Fabric IP For High-Performance, Power-Efficient SoC Designs (Monday Jul. 24, 2006)
  ARM has secured multiple licensees for the new Fabric IP which enables the rapid assembly of SoC designs
  
  
• ARM Enhances Reference Methodologies With Library Views And Pre-Compiled Rams (Monday Jul. 24, 2006)
  ARM Enhances Reference Methodologies With Library Views And Pre-Compiled Rams
  
  
• Evatronix Releases Updates to R8051XC Microcontroller Cores (Monday Jul. 24, 2006)
  Evatronix S.A., the silicon Intellectual Property (IP) provider, has announced technical updates to its R8051XC microprocessor cores used in a wide range of applications including wireless transmission control chips (supporting ZigBee or Bluetooth protoco
  
  
• Deal enables MOSIS to offer XAP 16-bit processors (Friday Jul. 21, 2006)
  Cambridge Consultants has teamed up with multi-project wafer (MPW) services provider, MOSIS, to enable royalty-free access to their XAP4 and XAP5 16-bit RISC processor cores
  
  
• Parallel processor firm enhances core for HD video (Friday Jul. 21, 2006)
  PACT XPP Technologies AG, a developer of a reconfigurable highly parallel processor, has redesigned its technology to produce the XPP-III version of its architecture and claimed that performance, for the first time, allows high definition video decoding w