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IP / SOC Products News

• Infineon and videantis announce 65nm platform verification with multi-standard video processing solution (Wednesday Jan. 24, 2007)
  The IC is based on multiple cores of the v-MP2000M multi-standard video engine. Due to its full programmability, the video architecture features video compression and decompression, e.g., H.264/AVC, MPEG-4, WMV9/VC-1, and MPEG-2, transcoding, and video enhancement functionality like scaling and blending.
  
  
• SLE, a Tundra Division, Offers High-Speed Interlaken Interconnect Protocol IP Core (Tuesday Jan. 23, 2007)
  Silicon Logic Engineering Develops Scalable IP Core for Next Generation Communications Equipment
  
  
• Denali PCI Express Product Passes First PCI Express 1.1 Compliance Testing in USA (Tuesday Jan. 23, 2007)
  Industry-Leading PureSpec Verification IP Product Helps to Ensure First-Pass Success in Compliance Tests
  
  
• MOSAID First to Market with Memory Controller and PLL Products for 65nm Process Technology (Monday Jan. 22, 2007)
  MOSAID Memorize offers the highest performance DDR SDRAM memory controller IP available on the market. Supporting DDR2 data rates up to 1066Mb/s, Memorize delivers DDR3 performance today. MOSAID's Maestro fractional-N PLL is a fully integrated, programmable, low power, high performance, Delta-Sigma Fractional-N PLL. It is optimized for line operated and battery powered applications where the system clock can operate at data rates as high as 3.2GHz.
  
  
• DAFCA Announces Commercial Silicon Success (Monday Jan. 22, 2007)
  DAFCA, Inc, the leading vendor of on-chip reconfigurable infrastructure and tools for in-system, at-speed silicon validation, announced today they achieved their first commercial silicon implementations, and landed their sixth customer, in the fourth quarter of 2006
  
  
• ARM Extends DesignStart Program with ARM926EJ Processor (Friday Jan. 19, 2007)
  The ARM DesignStart program was established to provide designers with the ability to evaluate ARM processors for use in their designs. The program enables fabless companies, from start-ups through to small and medium size organizations, to do the majority of their design activities, including SoC integration and verification, software development and chip layout, prior to obtaining a full ARM Processor Foundry Program License.
  
  
• Chaos creates nonlinear signal processing IP (Thursday Jan. 18, 2007)
  The startup is marketing the algorithms as semiconductor intellectual property to be incorporated into chips to improve the effective signal-to-noise ratio of DSL modems and consequently improve their range, data rate or power requirements.
  
  
• Certicom Launches Suite B Hardware Security Power Bundle to Help Developers Leverage the Strong Security of Elliptic Curve Cryptography in Silicon (Wednesday Jan. 17, 2007)
  Suite B is the set of cryptographic algorithms recommended by the National Security Agency (NSA) to secure classified and unclassified communications. The private sector is also beginning to implement the Suite B algorithms in products and services as Suite B has redefined what is considered industry best practice for cryptographic implementations
  
  
• Barco Silex presents JPEG2000 encoder core optimized for digital cinema & broadcasting (Tuesday Jan. 16, 2007)
  The core architecture offers a flexible and high-speed solution in a cost-effective, single-chip FPGA. It is able to sustain the high encoding requirements of the large DCI (Digital Convergence Initiative) and broadcasting frame formats, including 2048 x 1080 and 4096 x 2160 resolutions and frame rates up to 48 frames per second.
  
  
• Faraday Launches Process-Customized IP Business for Foundry-Related IP (Monday Jan. 15, 2007)
  Faraday provides the Process-customized IP services to the generic CMOS processes, ranging from 0.18um to 65nm, and the specific special processes, such as CIS, and High Voltage process.
  
  
• Denali Announces Comprehensive PCIe 2.0 Design and Verification IP Suite (Monday Jan. 15, 2007)
  PureSpec support of the PCI Express Base 2.0 specification includes dynamic link speed management, link retraining, inferred electric idle, Access Control Service (ACS), and Functional-Level Reset (FLR). Preliminary support for the proposed multi-root hierarchy IOV and Address Translation Services specifications is also available.
  
  
• Arasan Announces New Gigabit Ethernet and Ethernet 10/100 Digital IP (Thursday Jan. 11, 2007)
  The digital controllers support 10/100/1000 in Full-duplex and 10/100 in Half-duplex. The Ethernet Controllers are completely IEEE 802.3 feature compliant but has many advantages for embedded use
  
  
• Athena announces availability of FFT processors for broadband (Wednesday Jan. 10, 2007)
  The Athena Atomic Signal Processing library now supports sampling rates ranging from kilohertz to 500 MegaSamples per second and beyond.Applications ranging from GPS filters to WiFi, WiMAX, and even space-based reconfigurable receivers, all find Athena's unique technology delivers unmatched results.
  
  
• Microtronix Announces New Enhanced Multi-port SDRAM Memory Controller IP Core (Wednesday Jan. 10, 2007)
  The latest version: doubles the number of system bus interface ports from two to four, provides support for Avalon pipelined burst cycles, and adds DDR2, Mobile DDR memory devices.
  
  
• Sonics Achieves Breakthrough in SoC Power Reduction (Tuesday Jan. 09, 2007)
  New Version of SonicsMX(R) SMART Interconnect(TM) Solution Reduces Idle Power for Complex SoCs to Microamps
  
  
• Imagination Technologies Showcases Fully Validated Multi-Standard HD Video Core at CES 2007 (Tuesday Jan. 09, 2007)
  The PowerVR MSVDX core is capable of decoding JPEG, MPEG-1, MPEG-2, MPEG-4, DivX, H.264, WMV8/9 and VC-1 at high definition resolutions and frame rates, including 720p, 1080i and 1080p, yet this multiple codec support has been implemented in an extremely efficient silicon area.
  
  
• Imagination Technologies Reveals Extended PowerVR SGX Graphics & Video Core Family (Tuesday Jan. 09, 2007)
  PowerVR SGX is a comprehensive graphics solution which, along with an industry-leading 3D graphics feature set that exceeds Khronos’ OpenGL 2.0 shader and Microsoft Vertex and Pixel Shader Model 3 requirements, also supports a full range of key video codecs and OpenVG 2D vector graphics acceleration.
  
  
• Imagination Technologies Showcases First OpenGL ES 2.0 Silicon at CES 2007 (Tuesday Jan. 09, 2007)
  Imagination Technologies Showcases First OpenGL ES 2.0 Silicon at CES 2007
  
  
• Xilinx and Apical Announce High Performance Video Enhancement IP for 1080p High Definition Displays (Monday Jan. 08, 2007)
  New Intellectual Property Core Leverages Key Capabilities of Cost-Effective Spartan-3 Platform
  
  
• Xilinx Demonstrates Industry's First Scalable 3-D Graphics Hardware Accelerator for Automotive Applications (Monday Jan. 08, 2007)
  Xylon The logi3D IP core from Xylon for OpenGL(R) ES API provides Tier One automotive electronic suppliers with a parameterizable and scalable solution, allowing flexibility for customized graphics applications based on specific OEM customer requirements.
  
  
• Ingot Systems Announces System Optimized PCI-Express x1 and x4 IP Cores (Monday Jan. 08, 2007)
  The IP7101 PCI-Express x1 IP Core and the IP7104 PCI-Express x4 IP Core are fully compliant with the PCI Express Base Specification v1.0a and v1.1, and are optimized for small die size, low-latency and very high payload bandwidth
  
  
• Wipro-NewLogic and Alereon Demonstrate Wireless USB Dual Role Device Solution (Monday Jan. 08, 2007)
  Based on Certified Wireless USB Technology from the USB Implementers Forum (USBIF), Wipro-NewLogic’s DRD MAC IP core acts as Wireless USB Device as well as Wireless USB Embedded Host. For the demo, one Wireless USB setup is configured as Embedded Host MAC (attached to a PC), the second is configured as a Device MAC (attached to a mobile handset). With this setup images and files are transferred through Wireless USB protocol.
  
  
• GDT introduces H.264 encoder Silicon IP (Thursday Jan. 04, 2007)
  GDT-H264EBH, highly integrated silicon IP core, is fully compliant to the emerging ISO/IEC 14496-10 (ITU-T H.264 or MPEG-4 Part10 /AVC) video coding standard. It is designed to offer maximum performance and compression quality at the lowest possible bit-rate.
  
  
• NovoBlox OTP Memory Qualifies at Jazz Semiconductor (Wednesday Jan. 03, 2007)
  Novocell Semiconductor announced that its NovoBlox OTP Memory has been silicon validated in Jazz Semiconductor’s CA18HR 0.18-micron process.
  
  
• Digital Core Design Announces Availability of DZ80, a 8-bit Microprocessor IP Core (Tuesday Jan. 02, 2007)
  It is an immediate substitute which is 100 percent compatible with pin, software in respect to a standard Z80. DZ80 is a single-chip 8-bit embedded processor dedicated for operation with fast (typically on-chip) and slow (off-chip) memories.
  
  
• ASIC Architect Announces Availability of Configurable AMBA 3 AXI Bridge for DDR Controller Cores (Tuesday Dec. 26, 2006)
  ASIC Architect Expands its DDR Offerings with AMBA© 3 AXITM Bridge for DDR Controller Cores
  
  
• Dolphin Integration Announces their new generation of CODEC providing a Signal to Noise Ratio of 100 dB (Thursday Dec. 21, 2006)
  a silicon area of 4.2 mm2 for the whole CODEC at no extra fabrication cost: 5 metal layers over a logic process at 0.13 um
  
  
• Array Electronics's DDR SDRAM Controller XS receives Xilinx AllianceCORE product certification (Thursday Dec. 21, 2006)
  Array Electronics, one of the leading european suppliers of Intellectual Property (IP) cores for the programmable logic market, has received AllianceCORE product certification from Xilinx for its DDR SDRAM Controller XS core, the flagship product of the family of DRAM memory controller IP cores of the company
  
  
• ARM Announces First Production-Ready DDR1 And DDR2 Memory Interface IP On TSMC 90-Nanometer Process (Tuesday Dec. 19, 2006)
  The ARM Velocity DDR1/2 memory interface is the first 90-nm production-ready IP to pass TSMC's IP quality assurance test
  
  
• Faraday Adds Fast Ethernet PHY and Controller Cores to its Licensable IP Portfolio (Tuesday Dec. 19, 2006)
  Faraday's 0.18µm ,and 0.13µm ,Fast Ethernet PHYs and the 10/100/1000 MAC digital IP cores have been production-proven and can be licensed immediately with design kits; the test chip of 90 nm PHY is expected to be available in February, 2007