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IP / SOC Products Articles

• The role of IP in the new generation of data center SoCs (Nov. 21, 2013)
  Exciting times are ahead for the next-generation of data center applications including network switches and compute servers. As ASSP suppliers implement a new class of SoCs supporting the latest SDN architectures and low-power micro servers, proven third-party IP will become necessary to help them quickly integrate the required functionality.
  
  
• An Introduction to Caskeid - Wireless Stream Synchronisation IP (Nov. 18, 2013)
  It’s a trend happening everywhere today: devices are going wireless and connecting to the Internet. And not just the ubiquitous smartphones, tablets and the smart TV either; add to this a growing list of consumer electronics products: refrigerators, ovens, games consoles, central heating systems, weather stations, radios and home stereo systems. Indeed the simple home stereo is struggling in the digital world. Countless inputs and control methods, incompatible interfaces, and way too many wires have created a home entertainment headache.
  
  
• Dealing with SoC metastability problems due to Reset Domain Crossing (Nov. 13, 2013)
  This article will review some of the conditions under which RDC occurs and propose some ways to deal with the problems that occur up front in the design phase.
  
  
• Display Driver with on-chip frame buffer and a scalable image compression engine (Nov. 11, 2013)
  A display Driver with on-chip frame buffer and a scalable image compression codec reaching visually lossless image quality is presented. The frame buffer compression codec can encode and decode up to eight pixels in one clock cycle. Integrating a whole frame buffer with RGB=888 or 10-10-10 bits into the display driver sharply reduces power dissipated between the AP chip and Display board. The existing working chips are manufactured by both UMC and TSMC 55nm high voltage CMOS process.
  
  
• How to specify and integrate successfully a measurement analog front-end including its power computation engine in an energy metering IC (Nov. 04, 2013)
  Based on the system specification of a typical smart meter, this article demonstrates the importance of carefully selecting the power metering IP solution so that its specification matches the standard requirements and copes with the application challenges. This article then pinpoints thoroughly the various issues that must be taken into account for the selection of the Silicon IP and helps identify the possible trade-offs between the performance of the Mixed-signal Front-end (MFE) and that of the Power and energy Computation Engine (PCE).
  
  
• Optimizing high-performance CPUs, GPUs and DSPs? Use logic and memory IP - Part I (Oct. 29, 2013)
  In this two-part article we describe available logic library and memory compiler IP and a typical EDA flow for hardening processor cores. Part I continues on to provide innovative techniques, using those logic libraries and memory compilers within the design flow, to optimize processor area.
  
  
• Meticom: Bridging FPGAs & MIPI-Enabled Devices (Oct. 23, 2013)
  Since MIPI as an interface was never intended to serve non-mobile applications, interfacing to FPGAs was never made a priority. This makes perfect sense, since the majority of FPGAs are not well-suited for use in high-volume mobile devices. On the other hand, FPGAs are quite common in medical, industrial, and automotive applications.
  
  
• Understanding - and Reducing - Latency in Video Compression Systems (Oct. 07, 2013)
  In the video world, latency is the amount of time between the instant a frame is captured and the instant that frame is displayed. Low latency is a design goal for any system where there is real-time interaction with the video content, such as video conferencing or drone piloting.
  
  
• Root Cause Analysis (RCA) of Soft Digital IP to improve IP Quality & Reusability (Oct. 07, 2013)
  
  
  
• Why using Single Root I/O Virtualization (SR-IOV) can help improve I/O performance and Reduce Costs (Oct. 07, 2013)
  In this paper, we will explore why designing systems that have been natively built on SR-IOV-enabled hardware may be the most cost-effective way to improve I/O performance and how to easily implement SR-IOV in PCIe devices.
  
  
• Verification challenges of ADC subsystem integration within an SoC (Oct. 01, 2013)
  An SoC designer is not required to know the deep design intricacies of any IP they are integrating into the SoC. So even from the perspective of an SoC designer, if the ADC is considered as a black box, there are many factors that decide the quality of performance of the ADC at the SoC level. We must take care of these factors.
  
  
• Using Sidense 1T-OTP in Power-Sensitive Applications (Sep. 30, 2013)
  There are alternatives to putting an OTP on-chip. The data can be held off-chip in some sort of programmable memory (or, perhaps, ROM). But this obviously has the disadvantage of requiring the cost of an extra chip. In smartphones it is not just the cost of another chip that is a problem, but the additional volume taken up by two chips. There is just not a lot of room inside a smartphone to fit everything.
  
  
• How Reusable IP Helps Reduce Product Design Cycles (Sep. 25, 2013)
  Reusing IP for product development has long been considered a promising option to deliver on most of these factors. In this column, we extend the concept of reusable IP to system design.
  
  
• Data acquisition systems and SoCs - A guide (Aug. 28, 2013)
  Data acquisition systems (abbreviated with the acronym DAS or DAQ) measure real world signals (temperature, pressure, humidity etc.) by performing appropriate signal conditioning on a raw signal (amplification, level shifting, etc.), and then digitizing and storing these signals.
  
  
• Building high performance interrupt responses into an embedded SoC design (Aug. 26, 2013)
  Executing interrupt service routines using conventional techniques requires many clock cycles and limits the ability of the designer to verify the SoC IP (intellectual property) during silicon testing. Here is a technique to make that easier.
  
  
• Designing a next-generation video interface with thunderbolt technology (Aug. 19, 2013)
  The traditional method for handling video data uses a USB interface for data and DisplayPort or HDMI for video output. With the introduction of the Thunderbolt interface, a system interface can be simplified with one connector for both data and video.
  
  
• Optimized Memory Accessing Through Coupling of Byte Enable Signals (Aug. 19, 2013)
  A comparison between the conventional memory access algorithm and the optimized algorithm for three different interfaces (Memory/ AHB/ IPS) is depicted below.
  
  
• Deriving design margins for successful timing closure (Aug. 15, 2013)
  SOC design timing performance degrades at every implementation step towards working silicon, so it is very important to have a right estimate of design frequency starting at the first stage of design implementation. Design margins make this possible.
  
  
• NVM memory: A Critical Design Consideration for IoT Applications (Aug. 12, 2013)
  The explosion of information that IoT devices will gather will require huge numbers of processors to process and manage the data from these IoT devices along with lots of low-cost, secure and reliable embedded non-volatile memory (NVM) for code storage, sensor trimming, device configuration, security keys and other storage functions. Virtually every one of the projected billions of IoT devices can use some amount of one-time programmable (OTP) memory.
  
  
• Design planning for large SoC implemention at 40nm - Part 3 (Aug. 12, 2013)
  A thorough exercise during physical architecture is the foundation for an efficient floorplan. It helps in reducing the overall turnaround time of the physical design phase. The broader prospective of the floorplan should be performed during the physical architecture phase, and the actual floorplaning phase should address the finer details of the floorplan, which impacts the physical design’s QoR.
  
  
• Free the Gadgets "Wireless Charging" (Aug. 12, 2013)
  Scientists are working on to develop methods to transmit power wirelessly that could cut the clutter and the hassle for carrying so many add-ons to a device. It may sound futuristic but not unrealistic.
  
  
• Design and Implementation of SD Host Controller IP Core (Jul. 29, 2013)
  This paper discusses a method to design an SD Host Controller IP Core that can be implemented on FPGAs. FPGAs are being widely deployed in various applications including industrial, commercial and military applications. Secure Digital is the most widely used portable memory standard. Its ultra-compact and rugged architecture, simple interface, high security, low power consumption, reliable operation and interoperability have made it the de-facto solution for portable storage. The IP Core is designed in accordance with SD Host Controller Specification 3.0 and implements many advanced features. The IP Core is developed, implemented and tested and the performance obtained matches industry standards.
  
  
• Navigating successful USB 3.0 compliance (Jul. 16, 2013)
  In this article, we explore important advanced preparations necessary to achieve USB compliance along with several key elements necessary to achieve prompt and effective USB 3.0 time-to-market.
  
  
• Design planning for large SoC implementation at 40nm - Part 2 (Jul. 15, 2013)
  Die size and power estimations are at the foundation of SoC implementation. The key is how early and how accurately can it be done. These two parameters are the main data point for making some critical decisions early on. Freezing the die size in the early phase of SoC development gives a solid foundation for the physical designer, but it is a challenge to come up with an optimum and realistic estimation.
  
  
• Silicon Intellectual Property - Delivering value to customers (Jul. 08, 2013)
  With many IP vendors in the market, the question is what really adds value to customers and help them choose the right vendor. How can an IP centric focus with services built around IPs can deliver value to customers?
  
  
• System Design in the Real World (Jul. 04, 2013)
  Debate rages over the correct methodology for SoC-based system design. Is it the traditional register transfer level (RTL) flow? Or is it high-level synthesis of a C-language behavioral model? What about an intellectual-property (IP) reuse methodology that minimizes any kind of code generation? Every expert has an opinion of how design teams ought to move from requirements definition to manufacturing.
  
  
• Understanding in-loop filtering in the HEVC video standard (Jun. 25, 2013)
  High Efficiency Video Coding (HEVC) is a video compression standard, a successor to H.264/MPEG-4 AVC (Advanced Video Coding), jointly developed by the ISO/IEC Moving Picture Experts Group (MPEG) and ITU-T Video Coding Experts Group (VCEG) as ISO/IEC 23008-2 MPEG-H Part 2 and ITU-T H.265.
  
  
• Link synchronization and alignment in JESD204B: Understanding control characters (Jun. 24, 2013)
  The transition to JESD204B as the digital interface of choice for high speed data converters is well underway. The JESD204 interface was released in its original form, JESD204, in 2006 revised to JESD204A in 2008, and in August 20011 revised once more to the current JESD204B.
  
  
• The Fundamentals of a SHA-256 Master/Slave Authentication System (Jun. 20, 2013)
  For more than 10 years, SHA-1 authentication has been used to effectively protect intellectual property from counterfeiting and illegal copying. As computer technology advances, customers are asking for an even higher level of security.
  
  
• DDR3: A comparative study (Jun. 20, 2013)
  This paper introduces the concept of DDR (Double Data Rate) memories and briefly delineates the features and functionalities of DDR3 memories in contrast with those of DDR2 memories, along with some basic guidelines to create an efficient DDR3 memory controller.