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Hynix Standardizes on SpringSoft's Verification Enhancement and Custom IC Design Solutions (Tuesday Oct. 26, 2010)
SpringSoft today announced that Hynix Hynix has standardized on the Verdi™ Automated Debug System and Laker™ Custom Layout Automation System.
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Synopsys Power-Aware Test Speeds Time to Volume Production at Realtek (Tuesday Oct. 26, 2010)
Synopsys today announced that Realtek Semiconductor Corporation, one of the world's leading network and multimedia IC providers, deployed Synopsys power-aware test to avoid power issues during test and accelerate production testing of its new digital media processor.
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Himax Standardizes on Synopsys Implementation, Verification and IP Solutions for Video SoC Products (Monday Oct. 25, 2010)
Synopsys today announced that Himax Technologies has selected Synopsys' Galaxy™ Implementation and Discovery™ Verification Platforms for its video system-on-chip (SoC) products.
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DOLPHIN Integration promotes a complete offering of detectors for on-the-fly checking (Friday Oct. 22, 2010)
The streams of data coming-out of present-day simulation systems during design checking is overwhelming for developers of Virtual Components (ViC) as well as integrators of Systems-on-Chip (SoC) and system architects embedding them into complete systems. The new technology of "detectors" enables parallel and automated data mining with cumulated know-how for circuit property analysis.
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Atrenta and TSMC Develop a Soft IP Qualification Flow (Friday Oct. 22, 2010)
Atrenta disclosed details today of a collaboration with TSMC to enhance the quality of delivered synthesizable IP using Atrenta's SpyGlass ® platform.
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Dolphin Integration launch their unique JAXpower structure for optimized power regulators (Friday Oct. 15, 2010)
Dolphin Integration now provide Integrators with solutions for optimizing Power Management Networks (PMN). Their JAXpower structure enables networking Power Management, whatever the SoC application schematics
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OCP-IP Partners with Duolog Technologies to Provide OCP Performance Analysis Solution (Tuesday Oct. 12, 2010)
Duolog Technologies and OCP-IP today announced that Duolog will provide its OCP-Tracker performance analysis tool free of charge to members of OCP-IP. Duolog’s OCP-Tracker tool allows designers of OCP-based systems to tune their system architectures to maximize performance.
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Recore Systems Selects Synopsys' Galaxy Implementation Platform for Reconfigurable SoC Development (Tuesday Oct. 12, 2010)
Recore Systems today announced that it has selected Synopsys’ Galaxy Implementation Platform for the implementation of reprogrammable, application-specific DSPs. These DSPs target ultra-low power stream processing applications such as digital Radio and TV, personal media players (PMPs) and navigation and infotainment systems.
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Dolphin Integration releases the evaluation kit for benchmarking at once Libraries and Memories (Friday Oct. 08, 2010)
Dolphin Integration offers the VEDA benchmark to assist SoC Integrators in their steadfast search for minimizing costs and maximizing the performances of each of their design.
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Elliptic Partners With Carbon Design Systems To Create Accurate System-Level Models (Tuesday Oct. 05, 2010)
Elliptic Technologies today announced that the company has partnered with Carbon Design Systems to translate Elliptic’s portfolio of security IP into system-level models which can be used by SoC architects, hardware and software teams that are working in SystemC environments.
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Synopsys Enhances Synplify FPGA Synthesis Software With up to 4X Faster Runtime and New Team-Design Capabilities (Monday Sep. 27, 2010)
Synopsys today announced the availability of enhancements to its Synplify Pro® and Synplify® Premier FPGA synthesis tools. The new features in the 2010.09 release shorten logic synthesis runtimes and enable faster post-netlist incremental design turns. Comprehensive support for Synopsys DesignWare® Library datapath and building blocks components enables the use of common RTL from prototype to production.
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Cadence Offers Optimized Implementation Methodology for Silicon Realization of New ARM Cortex-A15 MPCore Processor (Monday Sep. 27, 2010)
Cadence today announced it is providing its customers an optimized implementation methodology for the new ARM(R) Cortex(TM)-A15 MPCore(TM) processor that enables them to start designing Cortex-A15 processor-based SoCs immediately.
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Imperas and Open Virtual Platforms (OVP) Initiative Announce Full Support for MIPS Technologies' MIPS32 1074K Coherent Processing System (Monday Sep. 27, 2010)
Imperas today released models of the new MIPS32® 1074K™ Coherent Processing System (CPS) from MIPS Technologies, Inc., including example virtual platforms incorporating both the MIPS32 1074Kc™ and 1074Kf™ cores and support for the cores in Imperas’ advanced software development tools.
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Richtek Adopts SpringSoft Laker Software for Custom Design and Layout of Power-Management ICs (Monday Sep. 27, 2010)
SpringSoft today announced that Richtek has standardized on its Laker Advanced Design Platform (ADP) for design entry, and Laker™ Custom Layout Automation System for custom chip design and implementation.
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Qualcomm defines format for 3-D chip stress (Thursday Sep. 23, 2010)
Qualcomm has teamed up with Synopsys to define a new data exchange format it believes could be critical for supporting 3-D chip stacks that use through silicon vias. Qualcomm has already gotten support from at least one foundry and one chip assembler for the so-called Stress Exchange Format.
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Mentor Graphics, GateRocket Collaborate on Integrated Solution to Streamline FPGA Verification-Through-Synthesis Flow (Monday Sep. 20, 2010)
GateRocket today announced a collaborative solution with Mentor Graphics that streamlines the verification-through-synthesis flow for advanced FPGA design.
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CLK Design Automation announces breakthrough acceleration for AOCV table generation (Monday Sep. 20, 2010)
CLK Design Automation Inc today announced breakthrough performance improvements in stage-based advanced on chip variation (AOCV) table generation with Amber Path FX. Amber Path FX SBOCV generates a full set of AOCV tables for a complete 882 cell TSMC 40 nm library in under 16 hours.
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DOLPHIN Integration and TexEDA Design announce their cooperation, delivering a complete and attractive EDA flow embedding SMASH as LaySim into LayTools (Friday Sep. 17, 2010)
Dolphin Integration SA and TexEDA Design Inc announce today that their EDA solutions for logic & mixed-signal simulation, and for custom integrated circuit design, have been closely coupled and bundled to enable a complete and consistent flow.
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Altium acquires Morfik to help electronics designers add cloud connectivity to anything (Thursday Sep. 16, 2010)
Altium has announced it intends to acquire Morfik Technology. Altium’s objective is to help electronics designers expand their role from designing the electronics in devices to the larger role of designing and engineering web-based ‘device ecosystems’.
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SMIC Adopts Cadence Silicon Realization End-to-End Product Line for 65-40nm Design (Thursday Sep. 16, 2010)
Cadence today announced that SMIC has adopted the Cadence Silicon Realization product line for advanced node, low-power designs.
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eMemory Standardizes on Synopsys FastSPICE for Circuit Simulation (Tuesday Sep. 14, 2010)
Synopsys today announced that eMemory Technology, Inc. has selected Synopsys' CustomSim™ solution for all of its circuit simulation needs. On a 45-nanometer (nm) embedded non-volatile memory, the CustomSim solution demonstrated up to 2 times faster simulation runtime compared to other commercial FastSPICE tools, and delivered results tightly correlated to silicon data.
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Aldec, HighRely and Leading FPGA Vendors Establish DO-254 Ecosystem (Monday Sep. 13, 2010)
Aldec and HighRely announce the establishment of a DO-254 ecosystem, including Aldec, HighRely and industry leading programmable logic vendors: Actel, Altera and Xilinx.
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Synopsys DFTMAX Compression Cuts Pin-Limited Test Cost by 95 Percent at Silicon Image (Wednesday Sep. 08, 2010)
Synopsys today announced that Silicon Image employed DFTMAX™ compression, an integral part of the Galaxy™ Implementation Platform, to significantly lower manufacturing test cost and time.
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Microsoft Xbox Development Team Uses SpringSoft's Verdi Debug Software to Slash Design Time (Tuesday Sep. 07, 2010)
SpringSoft today announced that the development teams behind the key processors in Microsoft Corp.’s Xbox product line have used its Verdi™ Automated Debug System to significantly reduce design time and manage new levels of complexity in the latest generation of chips.
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Magma Delivers Hierarchical Reference Flow for the Common Platform Alliance's 32/28-nm Low-Power Process Technology (Wednesday Sep. 01, 2010)
Magma® Design Automation today announced the availability of a proven hierarchical RTL-to-GDSII reference flow for the Common Platform™ alliance's 32/28nm low-power process technology.
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Mentor Graphics Collaborates with GLOBALFOUNDRIES to Provide Easier Debugging Capability to IC Designers (Thursday Aug. 26, 2010)
Mentor Graphics today announced it has collaborated with GLOBALFOUNDRIES to create a facility called Graphical Design Rule Manual (GDRM) that helps IC designers rapidly debug layout design rule violations by integrating the Calibre® RVET results viewing environment with GLOBALFOUNDRIES' electronic design rule manuals.
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OCP-IP Delivers Transaction Generator Package (Tuesday Aug. 24, 2010)
OCP-IP today announced the availability of a Transaction Generator (TG), which is a transaction level (TL) SystemC simulator for benchmarking network-on-chips (NoCs) used in multiprocessor system-on-chip (SoC) applications.
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Winbond Adopts SpringSoft Laker Layout and Routing Systems for Design of High Performance, Low Power Memory Chips (Tuesday Aug. 24, 2010)
SpringSoft today announced that Winbond Electronics Corporation, a leading global supplier of semiconductor memory solutions headquartered in Taichung, Taiwan, has adopted the Laker™ Custom Layout Automation System including the Laker digital routing solution.
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STARC, Calypto and Virage Logic Break New Ground With Industry's Lowest Power Design Flow (Tuesday Aug. 24, 2010)
Calypto today announced its collaboration with Virage Logic and STARC to dramatically reduce on-chip SoC power. Extending its ongoing, independent efforts with STARC and Virage Logic, the multi-technology collaboration resulted in the development of a seamless flow for designs with various functional modes that control multiple on-chip power domains to achieve dramatic power savings. Initial results show up to 50 percent dynamic power reduction and up to 40 percent leakage power reduction in embedded SoC memories using Calypto's PowerPro MG tool and Virage Logic's SiWare(TM) Memory compilers.
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OCP-IP Provides Virtual Platform Leveraging Advanced OCP SystemC TLM Modeling Kit (Monday Aug. 23, 2010)
OCP-IP and CircuitSutra along with Imperas today announced the availability of a Virtual Platform Demo created utilizing OCP-IP’s advanced Modeling Kit.