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FPGA / CPLD Articles

• Debugging FPGA-based video systems: Part 2 (Jun. 03, 2013)
  In Part 2 of this series from Digital Video Processing For Engineers, Andrew Draper describes some of the strategies for debugging an FPGA-based video system to be sure it reliably delivers the necessary video streams in real time. Part 2: Clocked and flow controlled video streams.
  
  
• Debugging FPGA-based video systems: Part 1 (May. 28, 2013)
  Andrew Draper describes some of the strategies for debugging an FPGA-based video system to be sure it reliably delivers video streams in real time. Part 1: Timing analysis and debugging.
  
  
• All eyes on Zynq SoC for smarter vision (May. 17, 2013)
  The Zynq All Programmable SoC, in tandem with new Xilinx tools and IP, forms the foundation for the next generation of embedded vision products.
  
  
• The TV Studio Becomes a System (May. 13, 2013)
  Change is sweeping across the video production studio. High-definition (HD), ultra-high-definition (UHD), video over coaxial cable (or “coax”), video over Ethernet, digital post-production: the gusts of change are relentless. And while the basic functions of the studio remain unchanged since the days when Walter Cronkite first turned his reassuring yet saturnine gaze toward a camera, the way these functions are implemented and the architectures in which they reside are all in directed turmoil.
  
  
• FPGAs offer cost-effective, flexible solutions for remote radio heads (Apr. 19, 2013)
  The newest generation of field programmable gate arrays (FPGAs) – manufactured at the proven 28nm process technology node – offer tighter integration, a reduced BOM costs and increased operational efficiency. By using off-the-shelf intellectual property (IP) and Xilinx 7 series FPGAs and Zynq-7000 All Programmable SoC devices, OEMs can meet shifting market demands while avoiding the huge upfront investment of $20 million or more required to spin a new, fixed architecture device.
  
  
• A Network for the Smart Grid (Apr. 04, 2013)
  Say the words Smart Grid, and many people will think first of the new electric meter that recently appeared outside their home. But ask a power engineer, and she will talk about the most profound change in electricity distribution since AC conquered DC.
  
  
• An introduction to offloading CPUs to FPGAs - Hardware programming for software developers (Mar. 08, 2013)
  An introduction to offloading CPUs to FPGAs – Hardware programming for software developers Grzegorz Gancarczyk, Maciej Wielgosz, and Kazimierz Wiatr 3/7/2013 12:07 PM EST Several factors are disrupting the traditional monopoly of microprocessors for being the chip of choice for C algorithms. These include the cost and accessibility of cross-compilation tools, the power and speed limitations of microprocessors, and the availability of more reliable building blocks. In this article, three university researchers break down the problem into understandable steps that the average developer can follow to determine if FPGAs are worth the (decreasing) bother and – if the answer is "yes" – how to go about it. This is based on hundreds of hours of class and lab testing. The authors are willing to share teaching materials, curricula, and advice with any certified university. If there is sufficient interest in this article, they will produce two follow-on articles going into more details with regard to lab work and cycle-accurate incremental improvement.
  
  
• Analyzing the Options in High-Bandwidth System Interconnect-or, Serial: It's Not Just for Breakfast (Mar. 07, 2013)
  Interconnect architecture within systems used to be so obvious. Physical constraints, such as chip boundaries and board edges, imposed a partitioning scheme on the system. And then standards, such as GPIB or USB for I/Os, and microprocessor buses for internal connections, defined the interconnect scheme. Beyond these standards, connections were usually asynchronous and point-to-point.
  
  
• FPGA debugging techniques to speed up pre-silicon validation (Feb. 11, 2013)
  This paper talks about some debugging techniques for FPGAs that can be adopted to speed up the validation process while at the same time highlighting some of their constraints. These debugging techniques can be used for the various challenges or issues faced during pre-silicon validation as discussed below.
  
  
• Getting your Zynq SoC design up and running using PlanAhead (Feb. 11, 2013)
  The Zynq-7000 All Programmable SoC is the first of a new class of Xilinx devices that marry a dual-core ARM Cortex-A9 processor with programmable logic on a single chip.
  
  
• Developing FPGA applications for Edition 2 of the IEC 61508 Safety Standard (Jan. 28, 2013)
  This article touches on the application of the IEC 61508 Edition 2 Safety Standard to FPGAs pertaining to methods, and it establishes the foundation of a guideline for a Safety Package allowing the certification of FPGA-based products in accordance to the functional safety recommendation of the IEC 61508 Edition 2 Safety Standard.
  
  
• The Era of 20 nm Systems Approaches (Nov. 20, 2012)
  Perhaps no semiconductor process has generated more controversy—before a single product has been shipped—than the 20 nm node. There was argument over whether the node would have to wait for production-ready EUV lithography. It did not: double-patterning, though expensive and restrictive on layout, has met the needs of the finest-resolution mask layers.
  
  
• Implementing digital processing for automotive radar using SoC FPGAs (Nov. 07, 2012)
  This white paper describes how an automotive radar system was built using digital processing segments with Altera’s rapid prototyping and development tool flow for digital signal processing (DSP) design, known as DSP Builder Advanced.
  
  
• Small Cells - How fast and how many? (Oct. 23, 2012)
  Small cells are low-powered radio access nodes that may operate in both the licensed and unlicensed spectrum and that have a range of 10 meters to 200 meters, as compared to macrocells, which might have a range of a few kilometres. Small cells have long existed in the network with the purpose of filling in coverage gaps. The recent resurgence in interest in these small cells is being driven primarily by market demand for higher network capacity to host existing and new data services.
  
  
• FPGA-based video surveillance comes of age (Oct. 15, 2012)
  Programmable FPGA devices are the perfect choice for interfacing with multiple high-resolution image sensors simultaneously...
  
  
• From Multicore to Many-Core: Architectures and Lessons (Oct. 11, 2012)
  Just as you were getting used to the idea of multicore processors in systems on chips (SoCs), the world is changing again. As several presentations at August’s Hot Chips Conference make clear, multicore is becoming many-core: the number of processor cores closely coupled at the hearts of SoCs is rising from 2 or 4 to 8, 16, or many, many more.
  
  
• How partial dynamic reconfiguration helped make an FSK demodulator (Oct. 03, 2012)
  The ability to reconfigure a portion of a Xilinx FPGA on the fly allowed a European research team to create a more dependable system.
  
  
• The Cloud, Big Data, and Your Next System Design (Sep. 26, 2012)
  
  
  
• Interfacing QDR-II+ Synchronous SRAM with high-speed FPGAs, part 2 (Sep. 18, 2012)
  Part 2 of this article deals with implementation of the QDR II+ controller in popular FPGAs using standard IP blocks.
  
  
• Are Your FPGA Designs Secure? (Sep. 14, 2012)
  An interesting question relating to embedded design security was posted recently on the Microcontroller Central LinkedIn group. The question asked if engineers considered design security, and if so, how they implemented it. I immediately thought this topic would be interesting in the context of FPGA designs, because we face just as many -- if not more -- challenges with regard to securing our designs as our microcontroller cousins.
  
  
• Case study: Using Spartan to support green energy development (Sep. 11, 2012)
  Product development for industrial applications involves extensive research and preparation in an environment of rolling deadlines and ever-evolving product specifications. While time-to-market for this sector may not be as short as it is for consumer electronics, products must ship quickly and with as many essential functions, features and potential hooks for the next generation as possible.
  
  
• What Your SoC Designer Might Not Tell You About Power Management (Aug. 20, 2012)
  System designers today are beneficiaries of the enormous effort that system-on-chip (SoC) designers have put into chip-level power management. But for systems to actually consume less energy, system design teams must know what their SoC’s power management actually does. They must have a power plan for the overall system. And they must have an accurate model of the use modes their system will experience at the hands of end users. None of these are easy tasks, but taken together they are still not enough.
  
  
• The basics of FPGA mathematics (Aug. 08, 2012)
  Let's take a look at the rules and techniques that you can use to develop mathematical functions within an FPGA or other programmable device
  
  
• Enabling error resilience throughout the embedded system (Jul. 11, 2012)
  
  
  
• Optimizing FPGAs for power: A full-frontal attack (Jun. 19, 2012)
  Power has become a primary factor in the ever-important search for the “perfect” FPGA for a given design. Power management is critical in most applications. Some standards specify maximum power per card or per system. As such, designers must consider power much earlier in the design flow than ever before—often starting with the selection of an FPGA.
  
  
• Accelerate partial reconfiguration with a 100% hardware solution (May. 28, 2012)
  In many modern applications such as video processing, minimizing FPGA reconfiguration time is critical in order to avoid losing too many images. Partial reconfiguration is a technique that allows users to reconfigure a small part of the FPGA without impacting logical elements around it.
  
  
• FPGA testing for DO-254 compliance (May. 22, 2012)
  This article describes several significant challenges that can be encountered when verifying FPGA pin-level requirements during board level testing under DO-254 guidelines. More importantly, this article proposes a methodology that augments board level testing to overcome these challenges.
  
  
• The growing use of programmable logic in mobile handsets (May. 18, 2012)
  The pace of innovation in the mobile handset industry has never been higher, with users continuing to demand more from these devices. Smart phones, tablets and other battery powered devices have evolved beyond communication devices and now offer personal assistance by unifying “always connected” features such as navigation, email, phone, Internet access and camera.
  
  
• 2D vs. 2.5D vs. 3D ICs 101 (Apr. 09, 2012)
  I see a lot of articles bouncing around the Internet these days about 2.5D and 3D ICs. The problem is that there’s a lot of confusion in this area. While chatting to people I find that they typically either know this stuff “inside and out” … or they are somewhat baffled and bewildered. Thus, I decided to pen a few words on the subject to explain the way in which I see things.
  
  
• Inside the Xilinx Kintex-7 FPGA: A closer look at the first FPGA to use HKMG technology (Apr. 06, 2012)
  TMSC's HPL NMOS and PMOS transistors, as seen in the Kintex-7 FPGA, are shown below. The two transistors are made using a gate-last process, where the TiN/HfO2/oxide gate dielectric is first deposited, followed by the deposition, patterning and etching of the sacrificial polysilicon gates. Silicon nitride sidewall spacers are then formed along the sides of the gates and are used to define the source/drain regions.