D&R Industry Articles | Most Popular | SoC News Alerts |

IP / SOC Products Articles

• Improving design turn around time on a complex SoC by leveraging a reusable low power specification (Feb. 25, 2008)
  This paper presents an approach to power design specification intent and associated enabled design methodologies that allow a scalable implementation of voltage islands.
  
  
• Enhanced Capacitor Cross Coupled Front-End (Feb. 21, 2008)
  This paper presents two approaches to improve the performance of RF low noise amplifiers (LNAs) and downconversion mixers. One approach is for noise enhancement and the other is for improving flatness of very wide range LNA
  
  
• Secure Your Security Key in On-Chip SRAM: Techniques to avoid Data Remanance Attacks (Feb. 18, 2008)
  Security protection in modern microcontroller’s logic devices with memories is based on the assumption that information from the memory disappears completely after erasing or when the power to the memory is removed.
  
  
• Designing digital video broadcast and wireless systems with common FPGA building blocks (Feb. 14, 2008)
  A digital communication system shares many similar building blocks that comprise a digital TV transmission system design. These key building blocks begin with channel coding and modulation techniques. It is these similarities that make it easier to take existing design blocks from one system and modify them for use in another one.
  
  
• IPGenius, an on-line IP generation platform (Feb. 14, 2008)
  We present an on-line tool for the generation of Configurable IP modules that can be used in Semiconductor devices. This tool allows the generation of customized IP modules, configured according to user requirements which are packaged and delivered to the end-user via the Internet.
  
  
• Building High-Quality, Mixed-Signal IP in 65-nm and Beyond (Feb. 11, 2008)
  This paper presents some key concepts necessary to design and build high-quality mixed-signal IP in 65‑nm or smaller geometries. The paper addresses design, layout, and verification techniques—with a focus on low-power design, reliability, and yield. Several design examples are presented, highlighting key techniques employed in the Synopsys® DesignWare® Mixed-Signal Intellectual Property (MSIP) portfolio.
  
  
• Software - The X factor (Feb. 07, 2008)
  This paper discusses the challenges faced by IP providers and/or SoC designers in providing appropriate software enabling customers to program their chips in the applications. Provision of such software is a critical success factor for many semiconductor businesses and this paper raises some of the issues together with some best practice example solutions.
  
  
• Understanding the LIN PHY (physical) layer (Feb. 07, 2008)
  The physical layer of the Local Interconnection Network is a key part of this automotive networking standard; it has unique attributes of which designers should be aware.
  
  
• UWB Time-interleaved ADC exploiting SAR (Jan. 31, 2008)
  The current technology trend for Analog-to- Digital Converters (ADCs) is particularly keen on power reduction, together with high-speed performance. The goal of the paper is to demonstrate that both the features can be achieved by a time-interleaved ADC architecture exploiting Successive Approximation (SA) algorithm.
  
  
• Mixed Signal Drivers for Ultra Low Power and Very High Power Applications (Jan. 28, 2008)
  Evolving niche markets, such as ICs for biomedical applications, are very challenging in respect to power consumption and on chip power dissipation, namely, wide range from ultra low power (ULP) functionality (<uW) where IC is battery powered, e.g. mobile micro transducers, to very high power (VHP, >5W), e.g. coded energy transfer from RFID¡¯s for remote sensing and animal tracking.
  
  
• Analog IP: The changing technology scene (Jan. 28, 2008)
  Those who have been observing last year’s activity in the analog IP space would readily infer the growing relevance and importance of Analog IP to the semiconductor development eco-system. Interestingly, the digital world needs more analog, and a healthy Analog IP eco-system is a critical enabler to innovation at the system-on-chip level.
  
  
• Ultra Low Power Designs Using Asynchronous Design Techniques (Welcome to the World Without Clocks) (Jan. 21, 2008)
  This paper presents challenges with the synchronous (clocked) designs and describes the techniques to overcoming the same with asynchronous (Clockless) design methodology. The paper proposes to redesign the synchronous interconnect to an asynchronous interconnect that should cater to tomorrow’s needs of high speed and low power. These circuits work on Handshaking techniques. If not today SOC industry will be forced driven to this methodology tomorrow.
  
  
• Analysis: ZSP800 and VZ.AudioHD platform (Jan. 16, 2008)
  Verisilicon just released a DSP targeting HD audio applications. Here's how it stacks up against offerings from Tensilica, CEVA, Analog Devices, and Texas Instruments.
  
  
• USB Host IP-Core Hardware and Software Concurrent Development (Jan. 10, 2008)
  This paper presents a based on behavioral synthesis design flow that allows high-quality hardware and software design of IP-Cores. The main flow's advantage is that it allows hardware and software to be developed concurrently, reducing design time.
  
  
• H.264 Baseline Decoder With ADI Blackfin DSP and Hardware Accelerators (Jan. 07, 2008)
  In this paper, architecture and implementation of H.264/AVC baseline decoder for D1 resolution at 30fps using ADI Blackfin DSP and Hardware accelerators in FPGA is described.
  
  
• Do the Math: Reduce Cost and Get the Right Communications System I/O Connectivity (Dec. 20, 2007)
  As the deployment of PCI Express (PCIe)-native systems becomes more prevalent, many of the commonly used communications system endpoint solutions are being redesigned for PCIe connectivity.
  
  
• Low Power Transport Demultiplexer for ATSC and DVB Broadcast Format (Dec. 17, 2007)
  In this paper, we developed low power transport demultiplexer to support MPEG-2 transport streams for ATSC and DVB digital broadcast standards. Novel window based packet identification (PID) and section filtering is presented to provide a cost effective and flexible solution.
  
  
• Designing DDR3 SDRAM controllers with today's FPGAs (Dec. 13, 2007)
  This article outlines the major differences between DDR3 and DDR2 SDRAM architecture and reviews them in the context of an FPGA-based reference design tested in hardware at 800 Mbps.
  
  
• Partitioning applications across multiple cores (Dec. 10, 2007)
  Multi-core mania has definitely hit the embedded networking market, but as the dust begins to settle it has become clear that many important architectural details need to be examined closely before decisions are made about how to partition applications across multiple cores.
  
  
• Case study of a complex video system-on-chip (Dec. 03, 2007)
  The efficient design of complex, multimedia-intensive, heterogeneous multiprocessing (HMP) systems-on-chip (SoCs) for inclusion in HDTVs and related consumer-oriented systems presents a daunting array of challenges. A collaborative effort among IC designers using CoWare's ESL tools and Sonics' SMX smart-interconnect IP designed for this class of SoCs enabled the rapid optimization and verification of the design aspects necessary to meet the critical architectural challenges.
  
  
• Pushing the Frontier in Managing Power in Embedded ASIC or SoC Design with PCI Express (Nov. 26, 2007)
  This paper will discuss some techniques applicable to PCI Express such as changing device power states in coordination with operating system, managing clocks and managing device drivers. In addition, this presentation will present a trade-off analysis between latency and clock frequency with respect to power consumption.
  
  
• Designing a CMOS synthesizer RFIC (Nov. 19, 2007)
  The three major building blocks in a modern, fully-integrated transceiver are a transmitter (TX), a receiver (RX), and a synthesizer. A synthesizer design is quite different from the TX or the RX. Both a TX and a RX have a higher analog content. The synthesizer design has significantly higher digital content. It challenges the designer's analog and digital skills.
  
  
• Using the ARM Cortex-R4 for DSP, part 1: Benchmarks (Nov. 19, 2007)
  BDTI recently completed a benchmark analysis of the ARM Cortex-R4 core and is now releasing the first independent signal processing benchmark results for this processor. In this article, we'll take a look at its benchmark results and compare its performance to that of other ARM cores (including the ARM11, another moderate-performance core) and selected competitors.
  
  
• OCP SoC instrumentation solutions involve more than just trace (Nov. 19, 2007)
  On-chip analysis can effectively improve our understanding of complex embedded systems, such as Open Core Protocol (OCP)-based architectures. For OCP level systems integration, real-time performance analysis is often a priority for getting products to market quickly, and embedded instrumentation analysis that can be used with emulators, prototypes, and production silicon can provide systems information and control that go beyond simulation based analysis
  
  
• Insights using NAND flash in portable designs (Nov. 12, 2007)
  As the raging success of Apple's iPod still rings in our ears, NAND flash memory is seen as the rising star of solid-state memory for portable and consumer applications.
  
  
• Design and implementation of Parallel and Pipelinined Distributive Arithmetic based Discrete Wavelet Transform IP core (Oct. 29, 2007)
  This paper presents an approach towards VLSI implementation of the Discrete Wavelet Transform for image compression. The design follows the JPEG2000 standard and can be used for both lossy and lossless compression. In Discrete Wavelet transform, the filter implementation plays the key role. The poly phase structure is proposed for the filter implementation, which uses the Distributive Arithmetic (DA) technique.
  
  
• Ensuring high-quality video communications (Oct. 22, 2007)
  As the migration to high definition (HD) picks up speed, video system designers are faced with new challenges related to bandwidth requirements, image quality, transcoding and digital media codec flexibility. These are difficult issues even for relatively closed systems that operate in proximity to each other.
  
  
• The Case for DDR-XAUI (Oct. 18, 2007)
  Recent developments in the networking and silicon markets are driving the support of multiple ports of 10 Gigabit Ethernet to the limit. High levels of integration dictate that large numbers of XAUI interfaces must be integrated in silicon to a level where silicon devices are bound by their external interface limitations rather then their internal bandwidth.
  
  
• Design considerations for integrated CMOS receivers (Oct. 15, 2007)
  To meet the demands for the multi-band, multi-mode wireless standards in the current market, a highly integrated wireless receiver (RX) is desired. CMOS technology has become the technology of choice for the integrated receiver design.
  
  
• The RapidIO High-Speed Interconnect: A Technical Overview (Oct. 11, 2007)
  Developers are seeking ways to consolidate interconnect layers across the system. Not only are they trying to more seamlessly connect chips, boards, and chassis, ideally they'd like to collapse the data and control planes into a single fabric.