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IP / SOC Products Articles

• General Partitioning Guidelines for Validation of Large ASIC Designs On FPGA (Feb. 11, 2013)
  Today's FPGAs have the capability to contain a complex and large system-level design. However, in some cases, there is a requirement for these designs to be partitioned among several FPGAs for validation or prototyping. But, splitting the design into several FPGAs can create various partitioning issues, especially for relatively large designs with complex connectivity. These issues could possibly be circumvented if certain guidelines are followed. This paper talks about the general partitioning challenges and the guidelines that can be followed to get past these issues
  
  
• Open-source hardware for embedded security (Feb. 05, 2013)
  Imagine you’re waiting in line, queuing to enter a major event. The ticket you have bought online is stored on your smart phone. As you swipe your phone over some designated area, an NFC connection is set up, your ticket is validated and the gates open to let you in. And the good thing is, that it all happened anonymously.
  
  
• Reap the benefits of a general-purpose interface USB 3.0 device controller (Jan. 23, 2013)
  Since its introduction in 2000, USB 2.0 has been the de-facto interface standard of the PC world. With a transfer rate of 480Mbps, it is lightning fast and served as an apt solution for many interfacing needs. However, with the rise in demand for higher data rate applications like HD video streaming and high capacity hard disks, the reign of USB 2.0 is slowly being replaced by its successor – USB 3.0.
  
  
• Using SoCs for portable medical equipment (Jan. 22, 2013)
  Portable medical electronics has seen tremendous growth and adoption in the recent years. More equipment variants are being introduced in the market by an increasing number of companies. The need of the hour is better mass producible designs which are low in complexity and provide acceptable performance so as to keep the cost of the device low. To achieve this, designers need to consider power efficiency, cost, form factor, and FDA certification of components, among other factors.
  
  
• Integrating large-capacity memory in advanced-node SoCs (Jan. 15, 2013)
  In today’s system-on-chip (SoC) designs, memory content can consume over 50% of chip area. In addition, the size of individual memories has grown to approximately 40 Mb of contiguous memory. This combined increase can significantly impact the overall power, performance, and area of the chip, as well as manufacturing yield. Successful integration of large-capacity memory in advanced-node SoCs requires the right approach.
  
  
• Four soft-core processors for embedded systems (Jan. 09, 2013)
  Since 2000, the folks at Realtime Embedded have concentrated on helping companies develop embedded systems used in advanced products. Their four primary focus areas are FPGA, Linux, virtual hardware, and multicore processing systems. Realtime Embedded is involved in customer and financed research projects, in house and on site, spanning a wide range of industries.
  
  
• The Case for Developing Custom Analog (Jan. 07, 2013)
  Increasingly, product managers are considering a custom Analog SoC as an effective way to drastically reduce BOM costs. What would have been considered a radical product innovation just a few years ago, is now viewed as a viable route as even where product volumes are considered low NRE costs can in fact be recovered in short period of time. Innovative SoC solutions are challenging but the benefits are compelling where risk can be mitigated by choosing a development partner with a clear understanding of all the system components and of the various technology options for the SoC implementation. In a recently issued paper, S3 Group’s experts talk about the advantages of custom SoCs and build a strong business case for investment in a SoC development.
  
  
• The Past, Present and Future of DDR4 Memory Interfaces (Dec. 14, 2012)
  The latest DDR4 SDRAM memory standard offers significant performance benefits for SoC designers. Graham Allan, senior product marketing manager for DDR at Synopsys, discusses some of the challenges that design teams face in making the change from DDR3.
  
  
• Vertical crosspoint memory supports ultra-low-power devices for Internet of Things (Dec. 14, 2012)
  With its widely varied smart devices, the Internet of Things (IoT) is creating a demand for microcontrollers made application specific by software instead of dedicated system on chip (SoC) designs.
  
  
• Introduction to USB -- Part III (Dec. 13, 2012)
  USB can connect a series of devices using a tiered star topology. The key elements in USB topology are the host, hubs, and devices.
  
  
• A Performance Architecture Exploration and Analysis Platform for Memory Sub-systems (Dec. 10, 2012)
  In this paper, we outline the various parameters that affect the memory sub-system performance and also introduce the Sensitivity Analysis and Feature Exploration methodologies to analyze the degree of impact of each of these parameters. This platform, when used at an early architectural exploration phase, provides valuable feedback to the memory device, controller and PHY architects to focus on optimizing the most critical parameters. We present a case-study to analyze a next generation mobile DRAM based memory sub-system using our proposed performance architectural exploration platform, and provide a ranking metric for all the parameters that affect the memory sub-system performance for key mobile applications.
  
  
• Debunking myths about analog IP at 28 nm (Dec. 04, 2012)
  The economics of system-on-chip development are objective and well understood. Industry-wide trends set the stage for integrating more functions into a SoC, which then drives the scaling down of process technology nodes. In the resulting product, all of the previous product’s functionality is implemented while more functional blocks are added to build increasingly complex functionality. This trend is not questioned - it is an axiom.
  
  
• Achieving maximum motor efficiency using dual core ARM SoC FPGAs (Dec. 03, 2012)
  Michael Parker of Altera Corp. describes how to use an ARM/FPGA-based SoC for real-time machine control algorithm operations. He also describes how the SoC can function as a network processor to link up to the real-time network protocols used in many industrial automation applications.
  
  
• Choosing serial interfaces for high speed ADCs in medical apps (Nov. 30, 2012)
  In medical applications such as MRI, ultrasound, CT scanners, and digital X-ray, high channel count analog-to-digital converters (ADCs) are used to sample large arrays of data.
  
  
• NVMe powers SSDs in the enterprise (Nov. 28, 2012)
  With the emergence of non-volatile memory express (NVMe), a scalable host controller interface specifically developed for PCIe SSDs, and a supporting ecosystem plus dedicated devices such as NVMe programmable flash controller chips, the potential of PCIe SSDs for enterprise computing applications can be fully realized.
  
  
• Universal Flash Storage: Mobilize Your Data (Nov. 26, 2012)
  Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.
  
  
• Maximizing battery life on embedded platforms - Part 4. Turning off peripherals and subsystems (Nov. 20, 2012)
  Some systems have very clever peripherals and they are not just there to fill up the available silicon space. So, use the peripheral system to your advantage. If you have a DMA engine and need to copy large amounts of data about then use it! You can either have the CPU go off and do something else in parallel during the transfer time or, if nothing else needs doing, put it to sleep and wake it up when the data is in place.
  
  
• Introduction to USB - Part I (Nov. 15, 2012)
  This chapter presents a quick introduction to USB. The first section in this chapter introduces the basic concepts of the USB specification Revision 2.0. The second section explores the data flow model. The third section gives details about the device operation. Lastly, the fourth section describes USB device logical organization. The full protocol is described extensively in the USB Specification Revision 2.0.
  
  
• Predicting PLL reference spur levels due to leakage current (Nov. 12, 2012)
  A simple model can be used to accurately predict the level of reference spurs due to charge pump and/or op-amp leakage current in a phased-locked loop system. Knowing how to predict these levels helps pick loop parameters wisely during the early stages of a PLL system design.
  
  
• JESD204B vs. Serial LVDS I/F for wideband data converter apps (Nov. 07, 2012)
  The JESD204A/B interface reduces the number of digital inputs/outputs between data converters and other devices, such as FPGAs and SoCs.
  
  
• Secure Mobile Payments - Protecting display data in TrustZone-enabled SoCs with the Evatronix PANTA Family of Display Processors (Nov. 05, 2012)
  Secure System-on-Chips (SoCs) based on ARM® TrustZone® technology enable both hardware and software components to be isolated as a secure subsystem within a complex SoC and as such focus on processing protected, sensitive and valuable assets, such as payment credentials, whenever these might be endangered with an attack, modification or capture. At the same time the main system software may be an open Rich OS platform that enables downloading and use of arbitrary third-party and non-trusted applications which can gain access to almost all system hardware elements.
  
  
• Driver Solutions for LED Backlighting (Oct. 30, 2012)
  White LEDs (WLED) are increasingly becoming the light source of choice for backlighting applications due to their attractiveness in power efficiency and form factor. This white paper looks into the design specifications and constraints for an LED driver for backlighting solutions. Architectural methods would be discussed to address these constraints.
  
  
• Memory solution addressing power and security problems in embedded designs (Oct. 22, 2012)
  Wireless monitoring devices and digital wallets are creating a new category of battery-powered system on chip (SoC) designs. This article will examine the memory requirements—static RAM (SRAM), read only (ROM), and non-volatile memory (NVM)—of these SoCs and offer an innovative solution to accommodate the new constraints of this category of design.
  
  
• Auto apps accelerated by triple-play graphics cores (Oct. 22, 2012)
  This article briefly introduces the i.MX6 family of processing devices from Freescale. In particular, we consider the Triple-Play graphics processing units (GPUs) featured in the i.MX6 devices and explains the advantages that result from using three specialized graphics engines. Also introduced are two companies that create human machine interfaces (HMIs) for automobiles using the i.MX6 hardware platform.
  
  
• Stretching the Dynamic Range of ADCs - A case study (Oct. 09, 2012)
  Whether your application is focused on wireless communications or instrumentation, the performance bottleneck is often the dynamic range of the analog-to-digital converter (ADC). Dynamic range is often a key parameter within signal processing systems and a shortfall can limit the quality and range of signals that can be received.
  
  
• System-on-chip technology comes of age (Oct. 08, 2012)
  This article describes the emerging importance of the SoC, its likely technological evolution and its potential impact on the semiconductor industry in a mobility driven age.
  
  
• The Challenges of USB 3.0 (Oct. 02, 2012)
  After a three-year teething period, USB 3.0 is finally mainstream. Microsoft and Apple support USB 3.0 in their latest releases of Windows and Mac OS X, respectively; Intel and AMD support USB 3.0 in their latest chipsets. This creates critical mass, which will cause USB 3.0 peripheral deployment to ramp significantly in the coming year.
  
  
• Pipeline AES S-box Implementation Starting with Substitution Table (Oct. 01, 2012)
  This paper is focusing on the most time consuming step of the AES algorithm. This step is a Non-Linear Byte Substitution that transforms some byte value into a new byte value through the use of an S-box Substitution Table. This table contains pre-computed inverted values for each of the 256 8-bit numbers (bytes) considered as elements of the Galois finite field GF(28).
  
  
• DRAM Controllers for System Designers (Sep. 24, 2012)
  Buried somewhere inside the system-on-a-chip (SoC) at the heart of your system is a DRAM controller—or maybe there are two, or four. They are carefully-crafted, tiny blocks of logic that quietly go about their business of connecting the internals of the SoC to external DRAM, requiring no attention from system designers. Or, they wreak havoc, wasting bandwidth, burning energy needlessly, and even allowing data to be corrupted.
  
  
• Viewpoint -- USB 3.0: Not just for wired apps (Sep. 24, 2012)
  The need to deliver faster, power efficient data transfers on every device is more evident than ever. NetGear, for example, recently demonstrated a commercially available Wi-Fi-AC router and adapter running at 1.2 gigabits per second (Gbps). Given that consumers want to move terabytes of video and photos through their homes and into the cloud., minimizing power consumption is the No. 1 design challenge.