180nm OTP Non Volatile Memory for Standard CMOS Logic Process
Small area rail clamp for FinFET
MIPI D-PHY Bidirectional 4 Lanes in Fujitsu (40nm)
InCore Calcite Series: 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing
ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
Intel in advanced talks to sell Altera to Silverlake
Why RISC-V is a viable option for safety-critical applications
Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
What should you consider when building an SoC?
Hardware Security Module (GRHSM) IP Core: Enhancing Security in Critical Systems
A Complete Overview of RISC-V Open ISA for Your Quick Reference
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