MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps, 2T/2L
IO I2C 3.3V in GF (22nm)
Dual 12-Bit 20 to 200MS/s 1.2V ADC, CMOS 90nm
Broadcast quality video encoder for all NTSC and PAL video standards
AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing
ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
Intel in advanced talks to sell Altera to Silverlake
Why RISC-V is a viable option for safety-critical applications
Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
What should you consider when building an SoC?
Hardware Security Module (GRHSM) IP Core: Enhancing Security in Critical Systems
A Complete Overview of RISC-V Open ISA for Your Quick Reference
© 2024 Design And Reuse
All Rights Reserved.
No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.
Suppliers, list your IPs for free.