MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps, 2T/2L
IO I2C 3.3V in GF (22nm)
Dual 12-Bit 20 to 200MS/s 1.2V ADC, CMOS 90nm
Broadcast quality video encoder for all NTSC and PAL video standards
Imagination takes efficiency up a level with latest D-Series GPU IP
Q.ANT and IMS CHIPS Launch Production of High-Performance AI Chips, Establish Blueprint for Strengthening Chip Sovereignty
sureCore PowerMiser IP enables KU Leuven chip for AI applications to achieve dynamic power saving of greater than 40%
Why RISC-V is a viable option for safety-critical applications
Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
What should you consider when building an SoC?
Hardware Security Module (GRHSM) IP Core: Enhancing Security in Critical Systems
A Complete Overview of RISC-V Open ISA for Your Quick Reference
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