DPA- and FIA-resistant Ultra High Bandwidth FortiCrypt AES IP core
Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)
LIN PHY
MIPI D-PHY Rx-Only 4 Lanes in GF (28nm, 12nm)
VeriSilicon unveils next-generation high-performance Vitality architecture GPU IP series
Crypto Quantique adds TRNG to its quantum-derived, side-channel protected PUF hardware IP block
ARM versus Qualcomm court case opens
Quantum Readiness Considerations for Suppliers and Manufacturers
A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
From Concept to Reality: Understanding the Cadence Analog IC Design Flow
Enhancing IoT System Performance with Smart Memory Partitioning
Enabling Massive AI Clusters with the Industry's First Ultra Ethernet and UALink IP Solutions
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