Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
Application Specific NPU for SR, NR
DDR5 PHY IP for TSMC N3P
13-bit, 80 MSPS Analog-to-Digital Converter IP Block
SkyeChip Joins Intel Foundry Accelerator IP Alliance
CFX 0.13μm eFuse OTP IP has been applied in the mass production of over 15,000 CMOS image sensors
VeriSilicon Launches the Industry-Leading Automotive-Grade Intelligent Driving SoC Design Platform
Optimizing 16-Bit Unsigned Multipliers with Reversible Logic Gates for an Enhanced Performance
Automating Hardware-Software Consistency in Complex SoCs
Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
HBM4 Boosts Memory Performance for AI Training
Using AI to Accelerate Chip Design: Dynamic, Adaptive Flows
Design IP Market Increased by All-time-high: 20% in 2024!
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