USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, N7, N6, N5, N3P)
Ultra-low-power 60 GHz radar-on-chip
Post-Quantum Cryptographic Processor
RISC-V-based AI IP development for enhanced training and inference
Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
CAST Adds New SafeSPI Controller to its Functional Safety IP Core Product Line
SLS Launches Industry-First USB 20Gbps Device IP Core
Last-Time Buy Notifications For Your ASICs? How To Make the Most of It
CANsec: Security for the Third Generation of the CAN Bus
Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning
Behind the Scenes - Introducing Xiphera's Board
Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
Redefining XPU Memory for AI Data Centers Through Custom HBM4
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