400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)
TSMC MIPI D-PHY Tx 2.5G and MIPI D-PHY Rx 2.5G (Automotive Interface IP)
I3C Lite Advanced Controller
GUC Joins Arm Total Design Ecosystem to Strengthen ASIC Design Services
QuickLogic Announces $6.575 Million Contract Award for its Strategic Radiation Hardened Program
Arm loses out in Qualcomm court case, wants a re-trial
Quantum Readiness Considerations for Suppliers and Manufacturers
A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
From Concept to Reality: Understanding the Cadence Analog IC Design Flow
Enhancing IoT System Performance with Smart Memory Partitioning
Enabling Massive AI Clusters with the Industry's First Ultra Ethernet and UALink IP Solutions
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