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Title Sign Up for SoC News Alert	Publication


How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs	Jul. 10, 2017

LTE Single Carrier DFT: Faster Circuits with Reduced FPGA LUT/Register Usage	Aug. 22, 2016

Floating-point FFT with Minimal Hardware	Aug. 10, 2015

Non-Power-of-Two FFT Circuit Designs Do Not Have to be Difficult	Feb. 09, 2015

Rethinking the FFT	Oct. 06, 2014

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