CryoCMOS IP to Unlock Quantum Computing
MIPI D-PHY Tx-Only 4 Lanes in SMIC (28nm)
Display Controller - LCD / OLED Panels (AXI4 Bus)
Securyzr Digital True Random Number Generator (TRNG) by Secure-IC, compliant with NIST SP800-90
Arm loses out in Qualcomm court case, wants a re-trial
Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Enhancements to Creonic's DVB-S2X IP Cores for Greater Flexibility and Performance
Quantum Readiness Considerations for Suppliers and Manufacturers
A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
From Concept to Reality: Understanding the Cadence Analog IC Design Flow
Enhancing IoT System Performance with Smart Memory Partitioning
Enabling Massive AI Clusters with the Industry's First Ultra Ethernet and UALink IP Solutions
© 2024 Design And Reuse
All Rights Reserved.
No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.
Suppliers, list your IPs for free.